ADE7758ARWRL datasheet(48/68 Pages) AD

48 / 68 page

ADE7758

Rev. A | Page 48 of 68

FREQUENCY

KNOWN?

YES

STEP 0

SET CFNUM/CFDEN

AND

VARCFNUM/VARCFDEN

STEP 1

SET XWG/XVAR/XVAG

TO LOGIC 0

STEP 2

SET LYCMODE

STEP 3

CHOOSE

ACCUMULATION TIME

(LINECYC)

STEP 4

SET MASK FOR

LENERGY INTERRUPT

STEP 5

SET UP SYSTEM FOR

ITEST, VNOM, PF = 1

STEP 6

READ FREQUENCY

STEP 7

RESET STATUS

STEP 8

READ ALL

XWATTHR AND

XVAHR AFTER

LENERGY

STEP 8A

CALCULATE XWG

STEP 8B

CALCULATE XVAG

STEP 9

WRITE TO XWG AND

XVAG

CALIBRATE WATT

AND VA @ PF = 1

STEP 10

SET UP TEST

SYSTEM

FOR ITEST, VNOM,

PF = 0

STEP 11

RESET STATUS

STEP 12

READ ALL XVARHR

AFTER LENERGY

INTERRUPT

STEP 13

CALCULATE XVARG

STEP 14

WRITE TO XVARG

STEP 15

CALCULATE

WH/LSB, VAH/LSB,

VARH/LSB

END

Figure 81. Gain Calibration Using Line Accumulation

Step 1: Set xWG, xVARG, and xVAG to Logic 0.

Step 2: Set up ADE7758 for line accumulation by writing 0x3F

to LCYCMODE. This enables the line accumulation mode on

the xWATTHR, xVAHR, and xVARHR (0x01 to 0x03) registers

by setting the LWATT, LVAR, and LVA bits, LCYCMODE[0:2]

(0x17), to Logic 1. It also sets the ZXSEL bits, LCYCMODE[3:5],

to Logic 1 to enable the zero-crossing detection on all phases for

line accumulation. Additionally, the FREQSEL bit,

LCYCMODE[7], is set to Logic 0 so that FREQ (0x10) stores

the line frequency. When using the line accumulation mode, the

RSTREAD bit of LCYCMODE should be set to 0 to disable the

read with reset mode.

Step 3: Set the number of half-line cycles for line accumulation

by writing to LINECYC (0x1C).

Step 4: Set the LENERGY bit, MASK[12] (0x18), to Logic 1 to

enable the interrupt that signals the end of the line cycle

accumulation.

Step 5: Set the test system for ITEST, VNOM, and unity power factor

(calibrate watt and VA simultaneously and first).

Step 6: Read the FREQ (0x10) register if the frequency is

unknown.

Step 7: Reset the interrupt status register by reading RSTATUS

(0x1A).

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