AD15700SLASHPCB datasheet(34/44 Pages) AD

34 / 44 page

REV. A

–34–

AD15700

While the ADC is performing a bit decision, it is important that

voltage transients not occur on digital input/output pins or

degradation of the conversion result could occur. This is particu-

larly important during the second half of the conversion phase

because the ADC provides error correction circuitry that can

correct for an improper bit decision made during the first half of

the conversion phase. For this reason, it is recommended that when

an external clock is being provided, it is a discontinuous clock

that is toggling only when BUSY is low or, more importantly,

that it does not transition during the latter half of BUSY high.

External Discontinuous Clock Data Read after Conversion

Though the maximum throughput cannot be achieved using this

mode, it is the most recommended of the serial slave modes.

Figure 22 shows the detailed timing diagrams of this method.

After a conversion is complete, indicated by BUSY returning low,

the result of this conversion can be read while both

CS_ADC and

RD are low. The data is shifted out, MSB first, with 16 clock

pulses and is valid on both the rising and falling edge of the clock.

Among the advantages of this method is that the conversion perfor-

mance is not degraded because there are no voltage transients on

the digital interface during the conversion process. Another advan-

tage is to be able to read the data at any speed up to 40 MHz,

which accommodates both slow digital host interface and the

fastest serial reading.

Finally, in this mode only, the ADC provides a daisy-chain feature

using the RDC/SDIN input pin for cascading multiple converters

together. This feature is useful for reducing component count

and wiring connections when desired as, for instance, in isolated

multiconverter applications.

An example of the concatenation of two devices is shown in

Figure 23. Simultaneous sampling is possible by using a common

CNVST signal. It should be noted that the RDC/SDIN input is

latched on the opposite edge of SCLK of the one used to shift

out the data on SDOUT. Therefore, the MSB of the “upstream”

converter just follows the LSB of the “downstream” converter on

the next SCLK cycle.

AD15700

NO. 1

(DOWNSTREAM)

AD15700

NO. 2

(UPSTREAM)

DATA

OUT

BUSY

OUT

BUSY

CS_ADC IN

CNVST IN

SCLK IN

RDC/SDIN

SDOUT

RDC/SDIN

CNVST

CS_ADC

SCLK

CS_ADC

SCLK

SDOUT

Figure 23. Two AD15700s in a Daisy-Chain Configuration

External Clock Data Read during Conversion

Figure 24 shows the detailed timing diagrams of this method.

During a conversion, while both

CS_ADC and RD are low, the

result of the previous conversion can be read. The data is shifted

out, MSB first, with 16 clock pulses and is valid on both the rising

and falling edge of the clock. The 16 bits have to be read before

the current conversion is complete. If that is not done, RDERROR

is pulsed high and can be used to interrupt the host interface to

prevent incomplete data reading. There is no daisy-chain feature

in this mode and RDC/SDIN input should always be tied either

high or low.

To reduce performance degradation due to digital activity, a fast

discontinuous clock of at least 25 MHz when impulse mode is

used, and 32 MHz when normal or 40 MHz when warp mode is

used, is recommended to ensure that all the bits are read during

the first half of the conversion phase. It is also possible to begin

to read the data after conversion and continue to read the last

bits even after a new conversion has been initiated. That allows

the use of a slower clock speed like 18 MHz in impulse mode,

21 MHz in normal mode, and 26 MHz in warp mode.

D13

D14

D15

CS_ADC

BUSY

SCLK

SDOUT

CNVST

EXT/

INT = 1

RD = 0

INVSCLK = 0

Figure 24. Slave Serial Data Timing for Reading (Read Previous Conversion during Convert)

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