−25˚C

Note 5: These parameters are limited by the pin to pin capacitance of the package.

Note 6: This is the analog signal slew rate above which the signal is distorted as a result of finite internal slew rates.

Note 7: All switches in the device are turned “OFF” by saturating a transistor at the disable node as shown in

Figure 5. The delay time will be approximately equal

Note 8: This graph indicates the analog current at which 1% of the analog current is lost when the drain is positive with respect to the source.

Note 9:

Molded DIP (N)

85˚C/W

Cavity DIP (D)

100˚C/W

Small Outline (M)

105˚C/W

LF11331/LF13331

DS005667-1

LF11332/LF13332

DS005667-13

LF11333/LF13333

DS005667-14

LF11201/LF13201

DS005667-15

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