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TPS62050, TPS62051

TPS62052, TPS62054, TPS62056

SLVS432D – SEPTEMBER 2002 – REVISED OCTOBER 2003

APPLICATION INFORMATION (continued)

Undervoltage Lockout

The undervoltage lockout circuit prevents the device from misoperation at low input voltages. It prevents the

converter from turning on the switch or rectifier MOSFET under undefined conditions.

Synchronization

If no clock signal is applied, the converter operates with a typical switching frequency of 850 kHz. It is possible to

synchronize the converter to an external clock within a frequency range from 600 kHz to 1200 kHz. The device

automatically detects the rising edge of the first clock and synchronizes to the external clock. If the clock signal is

stopped, the converter automatically switches back to the internal clock and continues operation. The switchover

is initiated if no rising edge on the SYNC pin is detected for a duration of four clock cycles. Therefore, the

maximum delay time can be 8.3 µs if the internal clock has its minimum frequency of 600 kHz. During this time,

there is no clock signal available. The device stops switching until the internal circuitry is switched to the internal

clock source.

When the device is switched between internal synchronization and external synchronization during operation, the

output voltage may show transient over/undershoot during switchover. The voltage transients are minimized by

using 850 kHz as an initial external frequency, and changing the frequency slowly (>1 ms) to the value desired.

The voltage drop at the output when the device is switched from external synchronization to internal

synchronization can be reduced by increasing the output capacitor value.

If the device is synchronized to an external clock, the power-save mode is disabled and the device stays in

forced PWM mode.

Connecting the SYNC pin to the GND pin enables the power-save mode. The converter operates in the PWM

mode at moderate to heavy loads and in the PFM mode during light loads maintaining high efficiency over a wide

load current range.

Power Good Comparator

The power good (PG) comparator has an open drain output capable of sinking typically 1 mA. The PG function is

only active when the device is enabled (EN = high). When the device is disabled (EN = low), the PG pin is pulled

to GND.

The PG output is only valid after a 250 µs delay after the device is enabled and the supply voltage is greater

than 2.7 V. Power good is low during the first 250 µs after shutdown and in shutdown.

The PG pin becomes active high when the output voltage exceeds typically 98.5% of its nominal value. Leave

the PG pin unconnected, or connect to GND when not used.

Low-Battery Detector (Standard Version)

The low-battery output (LBO) is an open drain type which goes low when the voltage at the low battery input

(LBI) falls below the trip point of 1.21 V

±1.5%. The voltage at which the low-battery warning is issued is adjusted

with a resistive divider as shown in Figure 20. The sum of the resistors R1 and R2 is recommended to be in the

100-k

Ω to 1-MΩ range for high efficiency at low output current. An external pullup resistor at LBO can either be

connected to OUT, or any other voltage rail in the voltage range of 0 V to 6 V. During start-up, the LBO output

signal is invalid for the first 500 µs. LBO is high impedance when the device is disabled. If the low-battery

comparator function is not used, connect LBI to ground. The low-battery detector is disabled when the device is

disabled. Leave the LBO pin unconnected, or connect to GND when not used.

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