PAM2804 datasheet(7/10 Pages) DIODES

7 / 10 page

PAM2804

Document number: DS36403 Rev. 3 - 2

7 of 10

www.diodes.com

September 2015

PAM2804

Application Information (cont.)

Since RDS(ON), quiescent current, and switching losses all vary with input voltage, the total losses should be investigated over the complete input

voltage range. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surrounding airflow

and temperature difference between junction and ambient. The maximum power dissipation can be calculated by the following formula:







)

MAX

(

Where TJ(MAX) is the maximum allowable junction temperature +125°C. TA is the ambient temperature and θJA is the thermal resistance from the

junction to the ambient. Based on the standard JEDEC for a two layers thermal test board, the thermal resistance

θJA of TSOT25 package is

250°C/W. The maximum power dissipation at TA = +25°C can be calculated by following formula:





250

125











Setting the Output Current

The internal feedback (FB) voltage is 0.1V (Typical). The output current is calculated as below:

LED 

The output Current is given by the following table.

RS(Ω)

ILED(mA)

0.286

350

0.143

700

0.1

1,000

As the input voltage approaches the LED forward voltage, the PAM2804 turns the P-Channel transistor continuously on. In this mode, the voltage

drop on LED is equal to the input voltage minus the voltage drop across the P-Channel transistor, Inductor and current resistor:





ILED

)

(

LEDDROP







Where RDS(ON) = P-Channel switch ON resistance, ILED = LED current, RL = Inductor DC Resistance, RS = Inductor DC Resistance.

Thermal Shutdown

When the die temperature exceeds +150°C, a reset occurs and the reset remains until the temperature decrease to +120°C, at which time the

circuit can be restarted.

PCB Layout Check List

When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the PAM2804. These items are

also illustrated graphically in Figure 1. Check the following in your layout:

1. The power traces, consisting of the GND trace, the SW trace and the VIN trace should be kept short, direct and wide.

2. Does the VFB pin connect directly to the current sense resistor? The current sense resistor to GND trace should be kept short, direct and wide.

3. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the internal power MOSFETs.

4. Keep the switching node, SW, away from the sensitive VFB node.

5. Keep the (

–) plates of CIN and COUT as close as possible.

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