Silan

Semiconductors

SC84510

HANGZHOU SILAN MICROELECTRONICS JOINT-STOCK CO.,LTD

Rev: 1.0

2000.12.31

4

Note:

1. All voltage in above table are compared with VSS.

2. All parameters in above table are tested under VDD=5V.

3. CLK & DATA output gates are open drains that connect to pull up resistors.

X1, X2, Y1, Y2 input impedance

0

1.0

2.0

3.0

4.0

5.0

5.0

UNIT:K

¡

MAX.

TYP.

MIN.

7.0

8.0

9.0

6.0

2.0

3.0

4.0

1.0

10.0

15.0

16.0

12.0

13.0

14.0

11.0

VOLTAGE (LIN)

10.0M

Parameter

Symbol

Min

Typ

Max

Unit

Oscillating Frequency

Fosc

34.3-10%

34.3

34.3+10% kHz

Key Debounce

Tkd

--

12

--

ms

Rising Edge Crossed Width Fosc=35KHz

Tr

14.3

--

--

µs

Falling Edge Crossed Width

Tf

14.3

--

--

µs

Mouse CLK Active Time

Tmca

--

42.9

--

µs

Mouse CLK Inactive Time

Tmci

--

42.9

--

µs

Mouse Sample DATA from CLK rising Edge

Tmdc

--

14.3

--

µs

System CLK Active Time

Tsca

--

42.9

--

µs

System CLK Inactive Time

Tsci

--

42.9

--

µs

Time from DATA Transition to Falling Edge of CLK

Tsdc

--

14.3

--

µs

Time from rising Edge of CLK to DATA Transition

Tscd

--

28.6

--

µs

Time to mouse Inhibit after the 11th CLK to ensure mouse does

not start another Transmission

Tpi

0

--

50

µs

The AC timings are measured under using 35KHz system clock signal.