SCC68681 datasheet(6/29 Pages) PHILIPS

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Philips Semiconductors

Product data

SCC68681

Dual asynchronous receiver/transmitter (DUART)

2004 Apr 06

BLOCK DIAGRAM

The SCC68681 DUART consists of the following eight major

sections: data bus buffer, operation control, interrupt control, timing,

communications Channels A and B, input port and output port. Refer

to Figure 2, ‘Block Diagram’.

Data Bus Buffer

The data bus buffer provides the interface between the external and

internal data buses. It is controlled by the operation control block to

allow read and write operations to take place between the controlling

CPU and the DUART.

Operation Control

The operation control logic receives operation commands from the

CPU and generates appropriate signals to internal sections to

control device operation. It contains address decoding and read and

write circuits to permit communications with the microprocessor via

the data bus buffer. The DTACKN output is asserted during write

and read cycles to indicate to the CPU that data has been latched

on a write cycle, or that valid data is present on the bus on a read

cycle.

Interrupt Control

A single active-LOW interrupt output (INTRN) is provided which is

activated upon the occurrence of any of eight internal events.

Associated with the interrupt system are the Interrupt Mask Register

(IMR) and the Interrupt Status Register (ISR), the Auditory Control

may be programmed to select only certain conditions to cause

INTRN to be asserted. The ISR can be read by the CPU to

determine all currently active interrupting conditions. When IACKN is

asserted, and the DUART has an interrupt pending, the DUART

responds by placing the contents of the IVR register on the data bus

and asserting DTACKN.

Outputs OP3–OP7 can be programmed to provide discrete interrupt

outputs for the transmitter, receivers, and counter/timer.

Timing Circuits

The timing block consists of a crystal oscillator, a baud rate

generator, a programmable 16-bit counter/timer, and four clock

selectors. The crystal oscillator operates directly from a crystal

connected across the X1/CLK and X2 inputs. If an external clock of

the appropriate frequency is available, it may be connected to

X1/CLK. The clock serves as the basic timing reference for the Baud

Rate Generator (BRG), the counter/timer, and other internal circuits.

A clock signal within the limits specified in the specifications section

of this data sheet must always be supplied to the DUART. If an

external is used instead of a crystal, X1 should be driven using a

configuration similar to the one in Figure 8.

The baud rate generator operates from the oscillator or external

clock input and is capable of generating 18 commonly used data

communications baud rates ranging from 50 to 115.2 k baud. The

clock outputs from the BRG are at 16

× the actual baud rate. The

counter/timer can be used as a timer to produce a 16

× clock for any

other baud rate by counting down the crystal clock or an external

clock. The four clock selectors allow the independent selection, for

each receiver and transmitter, of any of these baud rates or external

timing signal.

Counter/Timer (C/T)

The counter timer is a 16 bit programmable divider that operates

one of three modes: Counter, Timer or Time Out mode. In all three

modes it uses the 16-bit value loaded to the CTUR and CTLR

registers. (Counter timer upper and lower preset registers).

• In the timer mode it generates a square wave.

• In the counter mode it generates a time delay.

• In the time out mode it monitors the receiver data flow and signals

data flow has paused. In the time out mode the receiver controls

the starting/stopping of the C/T.

The counter operates as a down counter and sets its output bit in

the ISR (Interrupt Status Register) each time it passes through 0.

The output of the counter/timer may be seen on one of the OP pins

or as an Rx or Tx clock.

The Timer/Counter is controlled with six (6) ‘commands’; Start C/T,

Stop C/T, write C/T, preset registers, read C/T value, set or reset

time out mode.

Please see the detail of the commands under the Counter/Timer

Communications Channels A and B

Each communications channel of the SCC68681 comprises a

full-duplex asynchronous receiver/transmitter (DUART). The

operating frequency for each receiver and transmitter can be

selected independently from the baud rate generator, the counter

timer, or from an external input.

The transmitter accepts parallel data from the CPU, converts it to a

serial bit stream, inserts the appropriate start, stop, and optional

parity bits and outputs a composite serial stream of data on the TxD

output pin. The receiver accepts serial data on the RxD pin,

converts this serial input to parallel format, checks for start bit, stop

bit, parity bit (if any), or break condition and sends an assembled

character to the CPU.

The input port pulse detection circuitry uses a 38.4 kHz sampling

clock derived from one of the baud rate generator taps. This results

in a sampling period of slightly more than 25

µs (assuming that the

clock input is 3.6864 MHz). The detection circuitry, in order to

guarantee a true change in level has occurred, requires that two

successive samples at the new logic level be observed. As a

consequence, the minimum duration of the signal change is 25

µs if

the transition occurs coincident with the first sample pulse. The

µs time refers to the situation in which the change of state is just

missed and the first change of state is not detected until 25

µs later.

Input Port

The inputs to this unlatched 6-bit port can be read by the CPU by

performing a read operation at address 0xD. A HIGH input results in

a logic ‘1’ while a LOW input results in a logic ‘0’. D7 will always

read as a logic ‘1’ and D6 will reflect the level of IACKN. The pins of

this port can also serve as auxiliary inputs to certain portions of the

DUART logic.

Four change-of-state detectors are provided which are associated

with inputs IP3, IP2, IP1 and IP0. A HIGH-to-LOW or LOW-to-HIGH

transition of these inputs, lasting longer than 25 to 50

µs, will set the

corresponding bit in the input port change register. The bits are

cleared when the register is read by the CPU. Any change-of-state

can also be programmed to generate an interrupt to the CPU.

All the IP pins have a small pull-up device that will source 1 to 4

µA

of current from VCC. These pins do not require pull-up devices or

VCC connections if they are not used.

Output Port

The 8-bit multipurpose output port can be used as a general

purpose output port, in which case the outputs are the complements

of the Output Port Register (OPR). OPR[n] = 1 results in

OP[n] = LOW and vice versa. Bits of the OPR can be individually set

and reset. A bit is set by performing a write operation at address

0xE with the accompanying data specifying the bits to be reset

(1 = set, 0 = no change). Likewise, a bit is reset by a write at

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