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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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QL8250 датащи(PDF) 8 Page - List of Unclassifed Manufacturers |
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QL8250 датащи(HTML) 8 Page - List of Unclassifed Manufacturers |
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8 / 49 page  ZZZTXLFNORJLFFRP 4XLFN/RJLF&RUSRUDWLRQ (FOLSVH,, )DPLO\ 'DWD 6KHHW5HY % Preliminary )LJXUH illustrates a QuickLogic PLL. )LJXUH 3// %ORFN'LDJUDP Fin represents a very stable high-frequency input clock and produces an accurate signal reference. This signal can either bypass the PLL entirely, thus entering the clock tree directly, or it can pass through the PLL itself. Within the PLL, a voltage-controlled oscillator (VCO) is added to the circuit. The external F in signal and the local VCO form a control loop. The VCO is multiplied or divided down to the reference frequency, so that a phase detector (the crossed circle in )LJXUH ) can compare the two signals. If the phases of the external and local signals are not within the tolerance required, the phase detector sends a signal through the charge pump and loop filter ( )LJXUH ). The charge pump generates an error voltage to bring the VCO back into alignment, and the loop filter removes any high frequency noise before the error voltage enters the VCO. This new VCO signal enters the clock tree to drive the chip's circuitry. F out represents the clock signal emerging from the output pad (the output signal PLLPAD_OUT is explained in 7DEOH ). This clock signal is meaningful only when the PLL is configured for external use; otherwise, it remains in high Z state. Most QuickLogic products contain four PLLs. The PLL presented in )LJXUH controls the clock tree in the fourth quadrant of its FPGA. QuickLogic PLLs compensate for the additional delay created by the clock tree itself, as previously noted, by subtracting the clock tree delay through the feedback path. For more specific information on the Phase Locked Loops, please refer to QuickLogic Application Note 58. 3//0RGHVRI2SHUDWLRQ QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output frequency— 7DEOH indicates the features of each mode. vco Filter FIN FOUT + - 1st Quadrant 2nd Quadrant 3rd Quadrant 4th Quadrant Clock Tree Frequency Divide Frequency Multiply 1 ._. 2 ._. 4 ._. 4 ._. 2 ._. 1 .._ PLL Bypass |
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