MPC8272CVRB datasheet(19/56 Pages) MOTOROLA

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MPC8272 PowerQUICC II™ Family Hardware Speciﬁcations

MOTOROLA

PRELIMINARY—SUBJECT TO CHANGE WITHOUT NOTICE

AC Electrical Characteristics

6.2

SIU AC Characteristics

Table 11 lists SIU input characteristics.

NOTE: PCI AC Timing

The MPC8272 meets the timing requirements of PCI Speciﬁcation

Revision 2.2. Refer to Section 7, “Clock Conﬁguration Modes” and “Note:

Tval (Output Hold)” to determine if a speciﬁc clock conﬁguration is

compliant.

Table 12 lists SIU output characteristics.

NOTE

Activating data pipelining (setting BRx[DR] in the memory controller)

improves the AC timing.

Figure 9 shows the interaction of several bus signals.

Table 11. AC Characteristics for SIU Inputs 1

1 Input speciﬁcations are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.Timings

are measured at the pin.

Spec Number

Characteristic

Value (ns)

Setup

Hold

Setup

Hold

MHz

100

MHz

100

MHz

sp11

sp10

AACK/TA/TS/DBG/BG/BR

3.5

0.5

sp11a

sp10

ARTRY/ TEA

0.5

sp12

sp10

Data bus in normal mode

3.5

0.5

sp13

sp10

Data bus in pipeline mode

2.5

0.5

sp15

sp10

All other pins

3.5

0.5

Table 12. AC Characteristics for SIU Outputs 1

1 Output speciﬁcations are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

Spec Number

Characteristic

Value (ns)

Max

Min

Maximum Delay

Minimum Delay

MHz

100

MHz

100

MHz

sp31

sp30

PSDVAL/TEA/TA

5.5

111

sp32

sp30

ADD/ADD_atr./BADDR/CI/GBL/WT

6.5

5.5

sp33

sp30

Data bus 2

2 To achieve 1 ns of hold time at 66.67/83.33/100 MHZ, a minimum loading of 20 pF is required.

6.5

5.5

0.5

sp34

sp30

Memory controller signals/ALE

5.5

sp35

sp30

All other signals

5.5

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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