MSC1210 datasheet(29/83 Pages) TI

29 / 83 page

MSC1210

SBAS203F − MARCH 2002 − REVISED NOVEMBER 2004

www.ti.com

The Register Map is illustrated in Figure 19. It is entirely

separate from the Program and Data Memory areas

mentioned before. A separate class of instructions is used

to access the registers. There are 256 potential register

locations. In practice, the MSC1210 has 256 bytes of

Scratchpad RAM and up to 128 SFRs. This is possible,

since the upper 128 Scratchpad RAM locations can only

be accessed indirectly. Thus, a direct reference to one of

the upper 128 locations must be an SFR access. Direct

RAM is reached at locations 0 to 7Fh (0 to 127).

FFh

255

128

FFh

80h

7Fh

0000h

Indirect

RAM

Direct

RAM

Scratchpad

RAM

SFR Registers

Direct

Special

Function

Registers

Figure 19. Register Map

SFRs are accessed directly between 80h and FFh (128 to

255). The RAM locations between 128 and 255 can be

reached through an indirect reference to those locations.

Scratchpad RAM is available for general-purpose data

storage. It is commonly used in place of off-chip RAM

when the total data contents are small. When off-chip RAM

is needed, the Scratchpad area will still provide the fastest

general-purpose access. Within the 256 bytes of RAM,

there are several special-purpose areas.

Bit Addressable Locations

In addition to direct register access, some individual bits

are also accessible. These are individually addressable

bits in both the RAM and SFR area. In the Scratchpad

RAM area, registers 20h to 2Fh are bit addressable. This

provides 128 (16

× 8) individual bits available to software.

A bit access is distinguished from a full-register access by

the type of instruction. In the SFR area, any register

location ending in a 0 or 8 is bit addressable. Figure 20

shows details of the on-chip RAM addressing including the

locations of individual RAM bits.

Working Registers

As part of the lower 128 bytes of RAM, there are four banks

of Working Registers, as shown in Figure 20. The Working

Registers are general-purpose RAM locations that can be

addressed in a special way. They are designated R0

through R7. Since there are four banks, the currently

selected bank will be used by any instruction using

R0—R7. This allows software to change context by simply

switching banks. This is controlled via the Program Status

Word register (PSW; 0D0h) in the SFR area described

below. Registers R0 and R1 also allow their contents to be

used for indirect addressing of the upper 128 bytes of

RAM. Thus, an instruction can designate the value stored

in R0 (for example) to address the upper RAM. The 16

bytes immediately above the R0—R7 registers are bit

addressable. So any of the 128 bits in this area can be

directly accessed using bit addressable instructions.

FFh

7Fh

2Fh

2Dh

2Eh

2Ch

2Bh

2Ah

29h

28h

27h

26h

25h

24h

23h

22h

21h

20h

1Fh

18h

17h

10h

0Fh

08h

07h

0000h

Direct

RAM

Bank 3

Bank 2

Bank 1

Bank 0

MSB

LSB

Indirect

RAM

Figure 20. Scratchpad Register Addressing

MSC1210 датащи(PDF) 29 Page - Texas Instruments

MSC1210 датащи(HTML) 29 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83

датащи скачать

ссылки URL