2M x 18 SigmaDDR-II SRAM—Top View

1

2

3

4

5

6

7

8

9

10

11

A

CQ

NC/SA

(72Mb)

SA

R/W

BW1

K

NC/SA

(144Mb)

LD

SA

SA

CQ

B

NC

DQ9

NC

SA

NC/SA

(288Mb)

K

BW0

SA

NC

NC

DQ8

C

NC

NC

NC

SA

SA0

SA

NC

DQ7

NC

D

NC

NC

DQ10

NC

NC

NC

E

NC

NC

DQ11

NC

NC

DQ6

F

NC

DQ12

NC

NC

NC

DQ5

G

NC

NC

DQ13

NC

NC

NC

H

Doff

ZQ

J

NC

NC

NC

NC

DQ4

NC

K

NC

NC

DQ14

NC

NC

DQ3

L

NC

DQ15

NC

NC

NC

DQ2

M

NC

NC

NC

NC

DQ1

NC

N

NC

NC

DQ16

SA

SA

SA

NC

NC

NC

P

NC

NC

DQ17

SA

SA

C

SA

SA

NC

NC

DQ0

R

TDO

TCK

SA

SA

SA

C

SA

SA

SA

TMS

TDI

11 x 15 Bump BGA—13 x 15 mm Body—1 mm Bump Pitch

Notes:

1. BW0 controls writes to DQ0:DQ8; BW1 controls writes to DQ9:DQ17.

2. A2, A7, and B5 are the expansion addresses.

GS8342T08/09/18/36BD-400/350/333/300/250

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Rev: 1.02 6/2012

3/35

© 2011, GSI Technology