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LT1619

1619fa

Here the input voltage ripple is filtered with R3, R4 and C1

so as to prevent the input ripple from falsely tripping the

LT1619 synchronization circuit. It is recommended that:

and

RR C

fOSC

4 1

≈

()

Implementation of Hysteretic UVLO

with External Synchronization

The UVLO circuit shown in Figure 10 operates down to

0.9V supply voltage. Algebraically the UVLO trip points

are:

S/S

GND

VIN

DRV

GATE

SENSE

LT1619

510k

51k

VIN

CLK

BAT85

2N2222

VIN UPPER TRIP POINT = 10V

VIN LOWER TRIP POINT = 8.4V

1619 F10

30k

8.2V

51k

–

51k

2N2222

Figure 10. Addition of Hysteresis UVLO While Synchronizing the

LT1619. Component Values Shown are for the Upper and the

Lower VIN Trip Points of 10V and 8.4V. In UVLO, the Gate Drive

is Disabled by Pulling the VC Pin Low. Disabling the Clock Shuts

Down the LT1619. If Not Synchronized, the Collector of Q2 Can

Be Tied to the S/S Pin and the Diode D1 Can Be Eliminated

The collector votage of Q2 is made about 1.4V at the VIN

lower trip voltage. This is necessary to prevent the UVLO

circuit from interfering with the feedback amplifier in the

LT1619.

Trickle Current Start from High Voltage Supplies

The low shutdown and idle mode quiescent supply cur-

rents of the LT1619 can be utilized to implement trickle

current start from high voltage input sources (such as a

36V to 72V telecom bus). The trickle current start-up

circuit in Figure 11 is modified from the UVLO circuit of

Figure 10. R10 is a high value resistor that charges the

storage capacitor C2 during start-up. Before VCC reaches

the upper UVLO trip point, Q2 holds the S/S pin low. The

LT1619 draws shutdown mode current (

≈15µA)fromVCC.

Q2 collector can also be tied to the VC pin through a diode

as in Figure 10. The LT1619 will then draw idle mode

quiescent current (

≈140µA) from VCC. R10 should be able

to charge C2 while supplying current to the UVLO circuit

and the LT1619. Maximizing R5 to R9 values reduces

power dissipation in R10.

When VCC crosses the upper UVLO threshold, the LT1619

starts switching and its current consumption increases.

Before the bootstrap takes over, the LT1619 draws its

current from C2. VCC ramps towards the lower UVLO

threshold. Increasing the value of C2 allows more time for

the bootstrap circuit to establish itself before the converter

enters undervoltage lockout.

S/S

GND

VIN

DRV

GATE

SENSE

LT1619

BOOTSTRAP

WINDING

VCC

HV VIN

1619 F11

R10

Figure 11. Trickle Current Start-Up with Bootstrapped VCC

and

UVLO Hysteresis

INH

INL

INH

INL









()





















–

|| R

()









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