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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LMX2542 датащи(PDF) 13 Page - National Semiconductor (TI) |
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LMX2542 датащи(HTML) 13 Page - National Semiconductor (TI) |
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13 / 22 page  1.0 Functional Description (Continued) 1.4 RF DIGITAL FILTERED LOCK DETECT A digital filtered lock detect status genrated from the RF phase frequency detector (PFD) is available on the LD pin (Pin 19) when the RF_LD bit (R0[21]) is set to 1. The LD output is therefore used to indicate the lock status of the RF synthesizer system. Furthermore, the LD output can be forced to GND at all times when the RF_LD bit is set to 0. When used as a lock detect output, the two inputs to the PFD, f N and fR, are first divided by 64. The lock detect digital filter then compares the difference between the phases of the inputs to the PFD to an RC generated delay of approxi- mately 10 ns. This delay is represented by t W in Figure 1 and Figure 2 below. If the phase error is less than 10 ns ( ∆t < t W) for 4 consecutive PFD comparison cycles, the RF PLL enters a locked state and the LD output is then forced HIGH. Once the phase error becomes greater than 10 ns ( ∆t > t W) the RF PLL falls out of lock and the LD is forced LOW ( ∼GND). The phase error in Figure 2 is measured on the leading edge. If the phase difference between the two inputs to the PFD is equal to 10 ns ( ∆t=t W), then the LD output becomes unpredictable. Refer to Section 2.2.4 for further details on how to program the digital filtered lock detect. Note: f R is the PFD input from the reference oscillator and fN is the PFD input from the programmable feedback divider (N counter). 20082406 FIGURE 1. Lock Detect Flow Diagram www.national.com 13 |
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