Rev: 1.12 7/2002

13/31

© 1999, Giga Semiconductor, Inc.

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com

Preliminary

GS84018/32/36AT/B-180/166/150/100

First Write

First Read

Burst Write

Burst Read

Deselect

R

W

CR

CW

X

X

WR

R

WR

X

X

X

CR

R

CW

CR

CR

Simplified State Diagram

Notes:

1. The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied Low.

and that ADSP is tied high and ADSC is tied low.

3. The upper and lower portions of the diagram together assume active use of only the Enable, Write and ADSC control inputs and assumes

ADSP is tied high and ADV is tied low.