PC87591S-VPC datasheet(94/437 Pages) NSC

94 / 437 page

Embedded Controller Modules (Continued)

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Revision 1.07

Block Length Counter Register (BLTCn)

A double-word, read/write register. Holds the current number of DMA transfers to be executed in the current block. BLTCn

is decremented by one after each transfer cycle. A DMA transfer may consist of one or two bytes according to TCS bit in

DMACNTLn register.

Location: Channel 0 - 00 FA1016

Channel 1 - 00 FA3016

Channel 2 - 00 FA5016

Channel 3 - 00 FA7016

Type: R/W

Note: Writing 0 to Block Length Counter field of BLTCn initializes the DMA for 221-1 transfers.

Block Length Register (BLTRn)

A double-word, read/write register. Holds the number of DMA transfers to be executed in the next block. Writing this register,

sets VLD bit in DMASTATn register to 1.

Location: Channel 0 - 00 FA1416

Channel 1 - 00 FA3416

Channel 2 - 00 FA5416

Channel 3 - 00 FA7416

Type: R/W

Note: writing 0 to Block Length field of BLTRn initializes the DMA for 221-1 transfers.

DMA Control Register (DMACNTLn)

A word-wide, read/write register that synchronizes the channel’s operation with the programing of the block transfer param-

eters. On reset, the implemented bits are initialized to 0.

The format of the DMACNTLn register is shown below.

Location: Channel 0 - 00 FA1C16

Channel 1 - 00 FA3C16

Channel 2 - 00 FA5C16

Channel 3 - 00 FA7C16

Type: R/W

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210

Name

Reserved

Block Length Counter

Bit

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210

Name

Reserved

Block Length

Bit

Name

Reserved

INCB

ADB

INCA

ADA

SWRQ

Reset

0000000

Bit

76543210

Name

BPC

DIR

IND

TCS

EOVR

ETC

CHEN

Reset

00000000

Bit

Description

CHEN (Channel Enable). Must be set to enable DMA operation on this channel

0: Channel disabled

1: Channel enabled

If CHEN bit in DMACNTLn register is cleared in all channels, the DMA clock is disabled to preserve power.

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