PC87591L datasheet(168/437 Pages) NSC

168 / 437 page

Embedded Controller Modules (Continued)

www.national.com

168

Revision 1.07

TWDT0 Control and Status Register (T0CSR)

The T0CSR register is a read/write register. It controls the operation and provides the status of the T0 timer. The non-re-

served bits of T0CSR are cleared (0) on reset.

Location: 00 FEE616

Type: R/W

WATCHDOG Count Register (WDCNT)

The WDCNT register is a byte-wide, write-only register. It holds the value loaded into the WATCHDOG counter when it is

touched and counts down from it. The WATCHDOG is started by the first write to the register. Each successive write restarts

the WATCHDOG counter. A write to WDCNT functions as a touch operation when WDSDME bit TWCFG register is cleared,

even if WDCNT is locked; in this case, the WATCHDOG counter is restarted using the value loaded in PRESET field before

WDCNT was locked (i.e., the new PRESET value is ignored). On reset this register is initialized to 0F16.

Location: 00 FEE816

Type: WO

WATCHDOG Service Data Match Register (WDSDM)

The WDSDM register is a byte-wide, write-only register. When WDSDME in TWCFG register is set, the WATCHDOG count-

ing restarts from the value in WDCNT, when WDSDM is written with 5C16. If any other data is written to this register, it trig-

gers a WATCHDOG signal. If RSDATA is written more than once per three WATCHDOG clock cycles, a WATCHDOG signal

is also triggered. When the WDSDME bit is cleared, a write to this register is ignored.

Location: 00 FEEA16

Type: WO

Bit

76543210

Name

Reserved

WDLTD

Reserved

RST

Reset

00000000

Bit

Description

RST (Reset). When set (1), forces the timer to restart counting in the next input clock rising edge. The bit is

cleared by the input clock rising edge, indicating that the counter resumed its automatic re-triggerable operation.

Writing 0 to this bit is ignored.

TC (Terminal Count). Indicates that the counter has reached zero (terminal count). This bit is cleared each time

the register is read. It is a read-only bit and data written to it is ignored.

Reserved.

WDLTD (WATCHDOG Last Touch Delay). The bit is set when the WDCNT is written. It is cleared after

WATCHDOG is updated. (After WATCHDOG is updated, it is safe to switch to Idle mode.)

7-4

Reserved.

Bit

76543210

Name

PRESET

Reset

00001111

Bit

Description

7-0

PRESET. Deﬁnes the counter preset value.

Bit

76543210

Name

RSDATA

Bit

Description

7-0

RSDATA.

PC87591L датащи(PDF) 168 Page - National Semiconductor (TI)

PC87591L датащи(HTML) 168 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL