PC87591L datasheet(145/437 Pages) NSC

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Embedded Controller Modules (Continued)

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Timer Interrupt Control Register (TnICTL)

The TnICTL register is a byte-wide read/write register. It contains the interrupt enable bit and associated interrupt pending

bits for the four timer interrupt sources. The TnICTL register format is shown below. The register is cleared on reset.

Location: MFT16 1: 00 FD8E16

MFT16 2: 00 FDAE16

Type: R/W

TAOUT (TAn Output Data). Contains the value of TAn output when TAn is used as a PWM output.

0: TAn is low

1: TAn is high

This bit is set and cleared by hardware and thus reﬂects the status of TAn. This bit can be read at any time. It

may be used to set the initial value of TAn output in PWM mode. Note that if the hardware attempts to toggle

this bit at the same time as software is writing to the bit, the software write takes precedence over the hardware

update. This bit has no effect when TAn is used as input.

Reserved.

Bit

76543210

Name

TDIEN

TCIEN

TBIEN

TAIEN

TDPND

TCPND

TBPND

TAPND

Reset

00000000

Bit

Description

TAPND (Timer Interrupt Source A Pending). When asserted, indicates that an interrupt condition (as shown

in Table 19 on page 140) has occurred. This bit can be set by either hardware or software.

This bit is cleared by a writing 1 to the respective bit in Timer Interrupt Clear register.

A write of 0 to this bit is ignored. The bit is cleared (0) on reset.

Timer Interrupt Source B Pending (TBPND). Same as TAPND but for a different condition, as shown in

Table 19.

Timer Interrupt Source C Pending (TCPND). Same as TAPND but for a different condition, as shown in

Table 19.

Timer Interrupt Source D Pending (TDPND). Same as TAPND but for a different condition, as shown in

Table 19.

TAIEN (Timer Interrupt A Enable).

0: No system interrupt occurs, but the associated pending flag TAPND is set

1: Enables a system interrupt based on the occurrence of a condition, as listed in Table 19

Note: The bit can be set or cleared by software at any time.

TBIEN (Timer Interrupt B Enable).

0: No system interrupt occurs, but the associated pending flag TBPND is set

1: Enables a system interrupt based on the occurrence of a condition, as listed in Table 19

Note: The bit can be set or cleared by software at any time.

TCIEN (Timer Interrupt C Enable).

0: No system interrupt occurs, but the associated pending flag TCPND is set

1: Enables a system interrupt based on the occurrence of a condition, as listed in Table 19

Note: The bit can be set or cleared by software at any time.

TDIEN (Timer Interrupt D Enable).

0: No system interrupt occurs, but the associated pending flag TDPND is set

1: Enables a system interrupt based on the occurrence of a condition, as listed in Table 19

Note: The bit can be set or cleared by software at any time.

Bit

Description

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