PC87591L datasheet(231/437 Pages) NSC

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Embedded Controller Modules (Continued)

Revision 1.07

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Flash Memory Status Register (FLSR)

This register provides the on-chip flash status. It is cleared (0016) on reset.

Location: 00 F8C216

Type: Varies per bit

Flash Memory Pre-Scaler Register (FLPSLR)

The FLPSLR register selects the pre-scaler divider ratio. FLPSLR defaults to (0016) on reset.

Location: 00 F8C416

Type: R/W

Bit

76543210

Name

Reserved

DERR

FMLFULL

FMBUSY

PERR

EERR

Reset

00000000

Bit

Type

Description

R/W1C EERR (Erase Error). Indicates an error in erasing the ﬂash by the core. It is cleared by writing 1 to it.

Writing 0 is ignored. This bit may be cleared only when the FMBUSY bit is cleared (0).

No program error detected (default)

An error occurred during erase

R/W1C PERR (Program Error). Indicates an error in writing to the ﬂash by the core. It is cleared by writing 1

to it. Writing 0 is ignored. This bit may be cleared only when the FMBUSY bit is cleared (0).

0: No program error detected (default)

1: An error occurred during program

2RO

FMBUSY.

0: The embedded flash is ready to accept operations

1: The embedded flash is not accessible since the PC87591x clocks are not ready or the embedded flash

is busy programing or erasing

3RO

FMLFULL (Double-Buffer Full). Indicates that the core can not write to the ﬂash since its buffer is full.

0: There is at least one word empty in the flash double buffer. If IENPROG is set (1), in the Flash Memory

Control register, an interrupt request to the ICU is active.

1: The double-buffer is full

R/W1C DERR (Data Loss Error). Indicates that a double-buffer overrun error has occurred during core access.

It is cleared by writing 1 to the DERR bit. Writing 0 is ignored. This bit may be cleared only when the

FMBUSY bit is cleared (0).

0: No data loss detected (default)

1: A write to a full buffer was detected

7-5

Reserved.

Bit

76543210

Name

Reserved

FTDIV

Reset

00000000

Bit

Description

3-0

FTDIV (Pre-Scaler Divider Value). This register should be configured based on the currently set core

frequency. See Table 33 on page 223 for details of required values.

7-4

Reserved.

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