PC87591L datasheet(224/437 Pages) NSC

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Pipelined Programing Cycles

Pipelined programing uses a word-wide double-buffer (for Main Block accesses) or a byte-wide double-buffer (for Informa-

tion Block accesses). Accesses should be word-wide or byte-wide, correspondingly; otherwise, results are undefined.

When the double-buffer is empty, the pipelined programing is initiated on a valid byte/word write to the on-chip flash. The

address of the transaction is the starting address. The Flash Timing Control automatically increments the address for the

next write to point to the next byte/word.

Pipelined programing is completed when the double-buffer is empty or on reaching the highest address within the row. On

completion, the busy indicator is turned off, any data in the double-buffer is discarded, an error indicator is turned on if an

error is detected, and the on-chip flash returns to standby.

Results are undefined when Main Block and Information Block accesses are interleaved while the double-buffer is not empty.

Low Power Read Operation Mode

The PC87591x supports low power read operation for the on-chip flash. When this is enabled (see “Flash Memory Control

enabled only when the core clock is below the following limit:

●

Below FMAX for Sections 0 and 1 controlled by LOWPWRF bit

4.16.4 Flash Access and Control

The flash may be accessed for read, program and erase of data in either the Main Block or Information Block. This section

describes the activities required to enable any of the operations from each of the access paths (Core, Host, JTAG).

Before an access path to the flash may be used, the PC87591x must be in a state that enables that path:

●

Core and Host Interface - Active in IRE, OBD or DEV environment (Information Block only for DEV environment).

For host write operations, the host must gain control of the ﬂash (HLOCK bit in SMCCST register must be set).

Any access (read or write) protection may override the requested access.

●

JTAG Interface - OBD or DEV environments with the JTAG Flash interface enabled.

Section 4.19 on page 248 provides details of the JTAG flash access. Section 4.16.5 on page 226 provides details of the

PROG environment bus. For all interfaces, read, program and erase protection flags may prevent the operations described

from being completed.

Note that during Erase and Program of the flash, an access to the flash is handled as follows:

●

Core read is delayed to the end of the read.

●

Core write to the Main Block or Information Block is ignored.

●

Core write to IBAI register is ignored.

●

Host reads or writes are ignored by the Flash interface and restarted by the host once the ﬂash program/erase is

completed.

If core activity is required during flash program or erase, make sure it executes from RAM or external memory before the

flash erase/programing begins.

Main Block Read

When the flash is not busy, read operations return the data in the accessed on-chip flash address. Either byte or word may

be read.

The SZCFG1 register defines the number of core bus cycles used to access Base Memory (see Section 4.1.11 on page 86

and “Static Zone Configuration Register (SZCFGn)” on page 85 for further details). The number of cycles that each access

requires, for each one of the zones, is defined in “Flash Read, Write and Erase Time” on page 222.

If the BIU configuration is identical in all environments, the access time to the on-chip flash Main Block and off-chip Base

Memory, for read operations, is the same. This allows cycle-by-cycle compatibility in IRE, OBD and DEV operating environ-

ments.

Information Block Read

Information Block data is read using an indirect access scheme. This information may be read by the core, through the JTAG

Interface or the Parallel Interface.

The core accesses the Information Block using indirect byte/word read access. To read from the Information Block:

●

The byte or word address must be stored in IBAI register (note that Information Block addresses are mapped from

000 as shown in Table 31 on page 221).; word addresses must be even.

●

Data byte/words must be read using a byte/word read operation from BD register.

The JTAG performs a read operation with an Information Block address attribute set. Only word read is allowed.

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