PC87591L datasheet(222/437 Pages) NSC

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Embedded Controller Modules (Continued)

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Flash Read, Write and Erase Time

The flash read access time affects the performance of the core. It is therefore recommended to configure the interface to

achieve the maximum performance allowed for the operation frequency. Table 32 lists the access time for each section of

the flash.

Notes:

●

Write cycle timing is not cycle-by-cycle emulated for off-chip Base Memory (SRAM).

●

For fast read operation, the respective BIU zone should be conﬁgured for fast read.

●

For n wait states, the respective BIU zone should be conﬁgured for normal read with n wait states. This provides an

n+2 cycles read throughput.

●

Sections 0 and 1 are also referred to as the Fast zone.

The Flash Timing Control, included as part of the PC87591x on-chip flash, controls the access time for read, write and erase

operations of the flash memory. This simplifies the handling and use of the flash by the user. To enable operation with var-

ious clock rates the Flash Timing Control includes a set of registers that enable the core to set the parameters. For more

details on the Flash Timing Control, see Section 4.16.3 on page 222.

4.16.3 Flash Interface States and Timing Control

The Flash Timing Control automates six states: Standby, Read, Program, Page Erase, Section Erase and Special Erase.

The widths of pulses used in flash operation are specified in registers and should be set by software based on the operation

frequency of the core clock.

●

Standby State

The ﬂash does not perform a read, program or erase operation. This is the default state when no operation is per-

formed; current consumption of the ﬂash is therefore minimal.

●

Read State

The ﬂash performs a read operation from either the Main Block or the Information Block. Host or core reads

through the core bus are extended to the required length based on the BIU SZCGF1settings. JTAG interface ac-

cess uses a busy ﬂag to indicate that the read operation is in progress. When the read is completed, the ﬂash re-

turns to Standby state.

●

Program State

The ﬂash programs a byte or word in either the Main Block or Information Block. This state is entered by a core or

host write (with the Program control bit set) or by a JTAG program command. While in this state, the busy indicator

is set. When the program operation is completed, if the verify is enabled, the data is veriﬁed and the error bits are

updated accordingly. During Program state, reset is ignored. During programing of the ﬂash, additional writes to

the ﬂash are ignored and reads are delayed until the ﬂash page programing is completed.

●

Page Erase State

The Page Erase state is entered by a core or host write or by a JTAG command when the Page Erase bit is set. An

address within the page speciﬁes which page is to be erased. While in this state, the busy indicator is set. When

the erase operation is completed and the veriﬁcation is enabled, the data is veriﬁed and the error bits are updated

accordingly. During Page Erase state, reset is ignored, additional writes to the ﬂash are ignored and reads are de-

layed until the ﬂash page erase is completed.

●

Section Erase State

The Section Erase state is entered by a core write or by a JTAG command when the Section Erase bit is set. An

address within the section speciﬁes which section is to be erased. While in this state, the busy indicator is set.

When the erase operation is completed, the data is veriﬁed and the error bits are updated accordingly. During Sec-

tion Erase state, reset is ignored, additional writes to the ﬂash are ignored and reads are delayed until the ﬂash

section erase is completed.

Table 32. Access Time for Flash Sections

Block Name

Section Number

Max Frequency1,2

1. See Section 7.5 on page 381 for the values of these parameters.

2. The Zone Conﬁguration register SZCFG1 should be used to set the access speed, based on the cur-

rent operation speed and minimum required access time.

Write Time

Erase Time

Main Block

Sections 0 and 1

FFMAX @ fast read

Approx. 20

µs,

as deﬁned in Table 33

Approx. 10 ms,

as deﬁned in Table 33

Information Block

Sections 0 and 1 FFMAX @ 3 clock cycles

Approx. 10 ms,

as deﬁned in Table 33

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