held low until V

6.9V. Any UVLO condition on the bootstrap capacitor will

disable only the high side output (HO).

LAYOUT CONSIDERATIONS

The optimum performance of high and low side gate drivers

cannot be achieved without taking due considerations during

circuit board layout. Following points are emphasized.

1.

A low ESR/ESL capacitor must be connected close to

the IC, and between V

and HS pins to support high peak currents being drawn

from V

2.

To prevent large voltage transients at the drain of the top

MOSFET, a low ESR electrolytic capacitor must be con-

nected between MOSFET drain and ground (V

3.

In order to avoid large negative transients on the switch

node (HS) pin, the parasitic inductances in the source of

top MOSFET and in the drain of the bottom MOSFET

(synchronous rectifier) must be minimized.

4.

Grounding considerations:

a) The first priority in designing grounding connections is

to confine the high peak currents from charging and

discharging the MOSFET gate in a minimal physical

area. This will decrease the loop inductance and mini-

mize noise issues on the gate terminal of the MOSFET.

The MOSFETs should be placed as close as possible to

the gate driver.

b) The second high current path includes the bootstrap

capacitor, the bootstrap diode, the local ground refer-

enced bypass capacitor and low side MOSFET body

diode. The bootstrap capacitor is recharged on the

cycle-by-cycle basis through the bootstrap diode from

the ground referenced V

charging occurs in a short time interval and involves high

peak current. Minimizing this loop length and area on the

circuit board is important to ensure reliable operation.

5.

The resistors on the RT1 and RT2 timer pins must be

placed very close to the IC and seperated from high

current paths to avoid noise coupling to the time delay

generator which could disrupt timer operation.

POWER DISSIPATION CONSIDERATIONS

The total IC power dissipation is the sum of the gate driver

losses and the bootstrap diode losses. The gate driver

losses are related to the switching frequency (f), output load

capacitance on LO and HO (C

and can be roughly calculated as:

P

2

There are some additional losses in the gate drivers due to

the internal CMOS stages used to buffer the LO and HO

outputs. The following plot shows the measured gate driver

power dissipation versus frequency and load capacitance. At

higher frequencies and load capacitance values, the power

dissipation is dominated by the power losses driving the

output loads and agrees well with the above equation. This

plot can be used to approximate the power losses due to the

gate drivers.

Gate Driver Power Dissipation (LO + HO)

V

20088905

The bootstrap diode power loss is the sum of the forward

bias power loss that occurs while charging the bootstrap

capacitor and the reverse bias power loss that occurs during

reverse recovery. Since each of these events happens once

per cycle, the diode power loss is proportional to frequency.

Larger capacitive loads require more current to recharge the

bootstrap capacitor resulting in more losses. Higher input

voltages (V

recovery losses. The following plot was generated based on

calculations and lab measurements of the diode recovery

time and current under several operating conditions. This

can be useful for approximating the diode power dissipation.

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