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AP3301 датащи(PDF) 10 Page - Diodes Incorporated |
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AP3301 датащи(HTML) 10 Page - Diodes Incorporated |
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10 / 16 page ![]() AP3301 Document number: DS38018 Rev. 4 - 2 10 of 16 www.diodes.com June 2016 © Diodes Incorporated AP3301 Operation Description (Cont.) Multi-Mode Operation The switching frequency curve in Figure 1 shows three operation modes. Burst Mode At no load and light load, the system will operate at burst mode. In burst mode, the switching frequency is fixed at about 22kHz to avoid audible noise. When the FB voltage is lower than 1.55V, the controller will not provide driving signal and the FB voltage will rise above 1.65V, then the driving signal will resume. By this control strategy, the system will eliminate a bunch of pulses and the power loss is reduced. QR Mode QR is the abbreviation of Quasi-Resonant which means that the power MOSFET is forced to turn on at valleys of VDS. With QR control, the switching power loss will be reduced by lower voltage stress of MOSFET. The VDS valley is detected by DEM pin through the voltage divider network of RDEM and RSOVP, once the divided voltage is less than 75mV during turning off internal of MOSFET, the counter in AP3301 will count it as one valley. At light load and medium load, the system will enter QR mode. As the load changes, the trend of the switching frequency in QR mode is modulated by AP3301 and following the internal arithmetic it is increased or decreased. In general when the turning-on valley changes, the frequency will jump to a new value, this frequency jump transits quickly and the turning-on valley changes between two neighboring valleys back and forth, this unstable condition introduces unacceptable audible noise. In benefit of Diodes proprietary “Valley Lock” technology, the turning on valley is locked and will not switch iteratively when the load is changed. Meanwhile, the frequency dithering function is built in to reduce EMI emission. As Figure 2 shows, switching frequencies between the power increase and power decrease line are a little different because of the inherent characteristic of valley-lock QR control, and it will result in a tiny difference in efficiency. When the load increases, the switching frequency is also increased, a frequency of 120kHz is set to clamp the maximum operating frequency, if this 120kHz is touched, the system will operate in normal DCM mode, and will return to QR if the load continues to increase. CCM Mode With the load increases, if the switching frequency decreases below 62kHz in valley1 mode, CCM mode is implemented to achieve high efficiency. Usually at low line voltage, the system will enter CCM mode at heavy load, while high line voltage the system may still operate at QR mode with 1st or 2nd valley on. Start-up Current and UVLO The start-up current of AP3301 is optimized to realize ultra low current (1 A typical) so that VCC capacitor can be charged more quickly. The direct benefit of low start-up current is the availability of using large start-up resistor, which minimizes the resistor power loss for high voltage AC input. An UVLO comparator is included in AP3301 to detect the voltage on VCC pin. It ensures that AP3301 can draw adequate energy from hold-up capacitor during power-on. The turn-on threshold is 15.8V and the turn-off threshold is 7.6V. Current Sense Comparator and PWM Latch The AP3301 operates as a current mode controller, the output switch conduction is initiated by every oscillator cycle and is terminated when the peak inductor current reaches the threshold level established by the FB pin. The inductor current signal is converted to a voltage signal by inserting a reference sense resistor RS. The inductor current under normal operating conditions is controlled by the voltage at FB pin. The relation between peak inductor current (IPK) and VFB is: S FB PK R V I 3 / ) 0 . 1 ( Moreover, FOCP with 1.8V threshold is only about tDELAY-FOCP delay, which can avoid some catastrophic damages such as secondary rectifier short test. Few drive cycles can alleviate the destruction range and get better protection. Leading-edge Blanking A narrow spike on the leading edge of the current waveform can usually be observed when the power MOSFET is turned on. A tLEB time leading- edge blank is built-in to prevent the false-triggering caused by the turn-on spike. During this period, the current limit comparator is disabled and the gate driver cannot be switched off. At the time of turning off the MOSFET, a negative undershoot (maybe larger than -0.3V) can occur on the SENSE pin. So it is strongly recommended to add a small RC filter or at least connect a resistor “R” on this pin to protect the IC (Shown as Figure 2). |
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