GS2972 datasheet(13/125 Pages) SEMTECH

13 / 125 page

GS2972 3G/HD/SD-SDI Serializer with Complete

SMPTE Audio & Video Support

Final Data Sheet

Rev. 9

GENDOC-047479

September 2013

13 of 125

www.semtech.com

VCO_VDD

Input Power

Power pin for VCO. Connect to +1.2V DC analog followed by an RC

filter (see Typical Application Circuit on page 120). VCO_VDD is

nominally 0.7V.

VCO_GND

Input Power

Ground connection for VCO. Connect to analog GND.

B9, B10

A_GND

Input Power

GND pins for sensitive analog circuitry. Connect to analog GND.

C4V/VSYNC

Synch-

ronous

with

PCLK

Input

PARALLEL DATA TIMING.

Please refer to the Input Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

TIM_861 = LOW:

The V signal is used to indicate the portion of the video field/frame

that is used for vertical blanking, when DETECT_TRS is set LOW.

The V signal should be set HIGH for the entire vertical blanking

period and should be set LOW for all lines outside of the vertical

blanking interval.

The V signal is ignored when DETECT_TRS = HIGH.

TIM_861 = HIGH:

The VSYNC signal indicates vertical timing. See Section 4.3 for

timing details.

The VSYNC signal is ignored when DETECT_TRS = HIGH.

C6, C7, C8PLL_GND

Input Power

Ground connection for PLL. Connect to analog GND.

C9, D9, E9,

CD_GND

Input Power

Ground connection for the serial digital cable driver. Connect to

analog GND.

C10, D10

SDO, SDO

Output

Serial Data Output Signal.

Serial digital output signal operating at 2.97Gb/s, 2.97/1.001Gbs,

1.485Gb/s, 1.485 /1.001Gb/s or 270Mb/s.

The slew rate of the output is automatically controlled to meet

SMPTE ST 424, SMPTE ST 292 and ST 259-C specifications according

to the setting of the RATE_SEL0 and RATE_SEL1 pins.

STANDBY

Input

Power Down input.

HIGH to power down device.

SDO_EN/DIS

Input

CONTROL SIGNAL INPUT.

Please refer to the Input Logic parameters in the DC Electrical

Characteristics table for logic level threshold and compatibility.

Used to enable or disable the serial digital output stage.

When SDO_EN/DIS is LOW, the serial digital output signals SDO and

SDO are disabled and become high impedance.

When SDO_EN/DIS is HIGH, the serial digital output signals SDO and

SDO are enabled.

D5, F7

RSV

−

These pins are reserved and should be connected to CORE_GND.

Table 1-1: Pin Descriptions (Continued)

Number

Name

Timing

Type

Description

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