GS1672 datasheet(21/116 Pages) SEMTECH

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GS1672 HD/SD-SDI Serializer with Complete SMPTE

Audio & Video Support

Data Sheet

53623 - 6

July 2011

21 of 116

Serial Output Intrinsic Jitter

tOJ

Pseudorandom

and SMPTE

Colour Bars HD

signal

–50

4, 6

tOJ

Pseudorandom

and SMPTE

Colour Bars SD

signal

–

200

400

GSPI

GSPI Input Clock FrequencyfSCLK

50% levels

3.3V or 1.8V

operation

––

MHz

–

GSPI Input Clock Duty Cycle

DCSCLK

60%

–

GSPI Input Data Setup Time

–

1.5

–

GSPI Input Data Hold Time

–

1.5

–

GSPI Output Data Hold Time

–

15pF load

1.5

–

CS low before SCLK rising

edge

50% levels

3.3V or 1.8V

operation

1.5

–

Time between end of

command word (or data in

Auto-Increment mode) and

the first SCLK of the

following data word - write

cycle

50% levels

3.3V or 1.8V

operation

PCLK

(MHz)

–

unlocked

445

13.5

74.2

27.0

37.1

74.25

13.5

148.5

6.7

Time between end of

command word (or data in

Auto-Increment mode) and

the first SCLK of the

following data word - read

cycle

50% levels

3.3V or 1.8V

operation

PCLK

(MHz)

–

unlocked

1187

13.5

297

27.0

148.4

74.25

53.9

148.5

CS high after SCLK falling

edge

50% levels

3.3V or 1.8V

operation

PCLK

(MHz)

–

unlocked

445

13.5

74.2

27.0

37.1

74.25

13.5

148.5

6.7

NOTES:

1. Input setup and hold time is dependent on the rise and fall time on the parallel input. Parallel clock and data with rise time or fall time greater

than 500ps require larger setup and hold times.

2. Single Ended into 75

Ω external load.

3. ORL depends on board design.

4. Alignment Jitter = measured from 100kHz to serial data rate/10.

5. Alignment Jitter = measured from 1kHz to 27MHz.

6. This is the maximum jitter for a BER of 10-12. The equivalent jitter value as per RP184 is 40ps max.

Table 2-4: AC Electrical Characteristics (Continued)

VCC = 3.3V ±5%, TA = -20°C to +85°C, unless otherwise shown

Parameter

Symbol

Conditions

Min

Typ

Max

Units

Notes

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