DS90C032B

LVDS Quad CMOS Differential Line Receiver

General Description

The DS90C032B is a quad CMOS differential line receiver

designed for applications requiring ultra low power dissipa-

tion and high data rates. The device is designed to support

data rates in excess of 155.5 Mbps (77.7 MHz) utilizing Low

Voltage Differential Signaling (LVDS) technology.

The DS90C032B accepts low voltage (350 mV) differential

input signals and translates them to CMOS (TTL compatible)

that may be used to multiplex outputs. The receiver also sup-

ports OPEN and terminated (100

Ω) input Fail-safe. Receiver

output will be HIGH for both Fail-safe conditions.

The DS90C032B provides power-off high impedance LVDS

inputs. This feature assures minimal loading effect on the

LVDS bus lines when V

The DS90C032B and companion line driver (DS90C031B)

provide a new alternative to high power pseudo-ECL devices

for high speed point-to-point interface applications.

Features

n Accepts small swing (350 mV) differential signal levels

n High Impedance LVDS inputs with power down

n Ultra low power dissipation

n 600 ps maximum differential skew (5V, 25˚C)

n 6.0 ns maximum propagation delay

n Industrial operating temperature range

n Available in surface mount packaging (SOIC)

n Pin compatible with DS26C32A, MB570 (PECL) and

41LF (PECL)

n Supports OPEN and terminated input fail-safe

n Conforms to ANSI/TIA/EIA-644 LVDS standard

Connection Diagram

Functional Diagram

Receiver Truth Table

ENABLES

INPUTS

OUTPUT

EN

R

R

OUT

LH

X

Z

All other combinations

V

H

of ENABLE inputs

V

L

Fail-safe OPEN

H

or Terminated

Dual-In-Line

DS100990-1

Order Number

DS90C032BTM

See NS Package

Number M16A

DS100990-2

March 1999

© 1999 National Semiconductor Corporation

DS100990

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