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SN0402002DBVR датащи(PDF) 19 Page - Texas Instruments |
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SN0402002DBVR датащи(HTML) 19 Page - Texas Instruments |
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19 / 31 page ![]() Monitored Voltage RP1 Pullup Voltage 1 2 3 4 5 6 MR Signal RP2 Pullup Voltage RSTSENSE Flag RSTVDD Flag R1 R2 TPS3106 CVDD TPS3103, TPS3106, TPS3110 www.ti.com SLVS363F – AUGUST 2001 – REVISED NOVEMBER 2015 10 Power Supply Recommendations These devices are designed to operate from an input supply with a voltage range between 0.9 V and 3.3 V. Though not required, it is good analog design practice to place a 0.1- μF ceramic capacitor close to the VCC pin if the input supply is noisy. 11 Layout 11.1 Layout Guidelines Follow these guidelines to lay out the printed-circuit-board (PCB) that is used for the TPS310x and TPS3110x family of devices. • Place the VDD decoupling capacitor close to the device. • Avoid using long traces for the VCC supply node. The VCC capacitor (CVDD), along with parasitic inductance from the supply to the capacitor, can form an LC tank and create ringing with peak voltages above the maximum VDD voltage. 11.2 Layout Example Figure 19. Example Layout (DBV Package) Copyright © 2001–2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: TPS3103 TPS3106 TPS3110 |
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