853006AG

www.icst.com/products/hiperclocks.html

REV. A AUGUST 18, 2004

11

Integrated

Circuit

Systems, Inc.

ICS853006

Figure 5 shows a schematic example of ICS853006. The

ICS853006 input can accept various types of differential input

signal. In this example, the inputs are driven by an LVPECL driv-

ers. For the ICS853006 LVPECL output driver, an example of

LVPECL driver termination approach is shown in this schematic.

Zo = 50

R10

50

+

-

3.3V

Zo = 50

R11

50

Zo = 50

Zo = 50

R6

50

C5 (Optional)

0.1u

(U1, 20)

R5

50

3.3V

R3

50

3.3V LVPECL

C1

0.1u

C2

0.1u

C6 (Optional)

0.1u

C3

0.1u

R2

50

3.3V

3.3V

(U1, 13)

(U1, 1)

C4

0.1u

Zo = 50

R4

50

(U1, 8)

R1

50

Zo = 50

R9

50

C7(Optional)

0.1u

U1

ICS853006

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

20

19

18

17

VCC

nQ0

Q0

nQ1

Q1

nQ2

Q2

VCC

PCLK

nPCLK

VBB

VEE

VCC

nQ3

Q3

nQ4

VCC

Q5

nQ5

Q4

+

-

Additional LVPECL driver termination approaches are shown in

the LVPECL Termination Application Note. It is recommended

at least one decoupling capacitor per power pin. The decoupling

capacitors should be physically located near the power pins.

For ICS853006, the unused output can be left floating.