Automotive 3-Phase MOSFET Driver

A4933

10

Allegro MicroSystems, LLC

115 Northeast Cutoff

Worcester, Massachusetts 01615-0036 U.S.A.

1.508.853.5000; www.allegromicro.com

• Setting PWML low turns off active low-side drives and turns on

the complementary high-side drives. This provides low-side–

chopped slow-decay PWM with synchronous rectification.

• PWMH and PWML may also be connected together and driven

with a single PWM signal. This provides fast-decay PWM with

synchronous rectification.

COAST Pin

An active-low input, which forces low all gate drive

outputs, GHx and GLx, and turns off all external FETs. This can

be used to protect the FETs and the motor in the case of a short

circuit. Using COAST does not clear any faults, so the fault flags

can still be decoded and the fault register data word can be read.

Because COAST turns off all the external FETs, it can also be used

to provide fast-decay PWM without synchronous rectification.

RESET Pin

This is an active-low input, and when active it

allows the A4933 to enter sleep mode. When RESET is held low

internal circuitry are disabled and the A4933 enters sleep mode.

During sleep mode, current consumption from the VBB and VDD

supplies is reduced to a minimal level. In addition, latched faults

and the corresponding fault flags are cleared. When the A4933 is

coming out of sleep mode, the protection logic ensures that the

gate drive outputs are off until the charge pump reaches its

correct operating condition. The charge pump stabilizes in

approximately 3 ms under nominal conditions.

RESET can be used also to clear latched fault flags without

entering sleep mode. To do so, hold RESET low for less then the

the outputs, such as short circuit detection or bootstrap capacitor

undervoltage, and also clears the fault register.

Note that the A4933 can be configured to start without any exter-

of an external resistor. The resistor value should be between

20 and 33 kΩ.

CCEN Pin

This input provides an override to allow both the high-

side and the low-side external FETs of any phase to be active at

the same time, enabling cross-conduction. As an extra level of

safety, cross-conduction can only occur when RDEAD is tied to

AGND and CCEN is set high. If the CCEN input is inadvertently

disconnected from the controller, an internal pull-down resistor

ensures that the outputs revert to a safe condition.

ESF Pin

This is the Enable Stop on Fault input. It determines the

action that is taken when certain faults are detected. See the Fault

Protection and Diagnostics section for details.

Table 1. Phase Control Truth Table

Inputs

Outputs

Comment

RDEAD

RESET

CCEN

COAST

PWMH

PWML

xHI

xLO

GHx

GLx

Sx

x

1

xxxx

0

0

L

L

Z

Phase disabled

x

1

x

11101

L

H

LS

Phase sinking

x

1

x

11110

H

L

HS

Phase sourcing

>0.2 V

1

xxxx

1

1

L

L

Z

Phase disabled

x

1

x

10101

L

H

LS

Sink; high-side PWM on other phases

x

1

x

10110

L

H

LS

Slow decay, SR; low-side recirculation

x

1

x

11001

H

L

HS

Slow decay, SR; high-side recirculation

x

1

x

11010

H

L

HS

Source; low-side PWM on other phases

x

1

x

10001

H

L

HS

Fast decay, SR

x

1

x

10010

L

H

LS

Fast decay, SR

AGND

1

x

11011

H

L

HS

Slow decay, SR; high-side recirculation

AGND

1

x

10111

L

H

LS

Slow decay, SR; low-side recirculation

x

0

xxxxxx

Z

Z

Z

Low power shutdown

x1x0x

x

x

x

L

L

Z

Coast

AGND

1

011111

L

L

Z

Phase disabled

AGND

1

111111

H

H

U

Cross-conduction

x = don’t care, HS = high-side FET active, LS = low-side FET active, Z = high impedance, both FETs off, U = undefined, SR = synchronous rectification