2

Functional Diagram

TRUTH TABLE

CLOCK UP

CLOCK

DOWN

RESET

PARALLEL

LOAD

FUNCTION

↑

H

L

H

Count Up

H

↑

L

H

Count Down

X

X

H

X

Reset

X

X

L

L

Load Preset Inputs

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,

↑ = Transition from Low to

High Level

ASYN.

MASTER

CLOCK UP

11

14

5

4

15

1

10

9

3

6

7

12

13

TERMINAL

P0

P1

P2

P3

LOAD

CLOCK DOWN

2

TERMINAL

COUNT UP

BCD (192)

BINARY (193)

OUTPUTS

BCD/BINARY

PRESET

ENABLE

PARALLEL

PL

RESET

COUNT DOWN

CD54/74HC192, CD54/74HC193, CD54/74HCT193