PCM1608KYSLASH2K datasheet(9/29 Pages) TI

9 / 29 page

PCM1608

SBAS164A

FIGURE 2. Power-On Reset Timing.

1024 System Clocks

Reset

Reset Removal

Internal Reset

2.4V

2.0V

1.6V

System Clock

Don’t Care

FIGURE 1. System Clock Timing.

SYSTEM CLOCK AND RESET

FUNCTIONS

SYSTEM CLOCK INPUT

The PCM1608 requires a system clock for operating the

digital interpolation filters and multilevel delta-sigma modu-

lators. The system clock is applied at the SCKI input (pin 38).

Table I shows examples of system clock frequencies for

common audio sampling rates.

Figure 1 shows the timing requirements for the system clock

input. For optimal performance, it is important to use a clock

source with low phase jitter and noise. The PLL1700 multi-

clock generator from Texas Instruments is an excellent

choice for providing the PCM1608 system clock.

The 192kHz sampling frequency operation is available on

DATA1 for VOUT1 and VOUT2, and DATA4 for VOUT7 and

VOUT8. It is recommended that VOUT3, VOUT4, VOUT5, and

VOUT6 be disabled when operating with fS = 192kHz. This

is done by setting the DAC3, DAC4, DAC5, and DAC6 bits

of Register 9 to a “1” state.

SYSTEM CLOCK OUTPUT

A buffered version of the system clock input is available at

the SCKO output (pin 39). SCKO can operate at either full

(fSCKI) or half (fSCKI/2) rate. The SCKO output frequency

may be programmed using the CLKE bit of Register 9. If the

SCKO output is not required, it is recommended to disable

it using the CLKE bit. The default is SCKO enabled.

POWER-ON AND EXTERNAL RESET FUNCTIONS

The PCM1608 includes a power-on reset function, as shown

in Figure 2. With the system clock active, and VDD > 2.0V

(typical, 1.6V to 2.4V), the power-on reset function will be

enabled. The initialization sequence requires 1024 system

clocks from the time VDD > 2.0V. After the initialization

period, the PCM1608 will be set to its reset default state, as

described in the Mode Control Register section of this data

sheet.

The PCM1608 also includes an external reset capability

using the RST input (pin 37). This allows an external

SAMPLING

FREQUENCY

128fS

192fS

256fS

384fS

512fS

768fS

8kHz

——

2.0480

3.0720

4.0960

6.1440

16kHz

——

4.0960

6.1440

8.1920

12.2880

32kHz

——

8.1920

12.2880

16.3840

24.5760

44.1kHz

——

11.2896

16.9344

22.5792

33.8688

48kHz

——

12.2880

18.4320

24.5760

36.8640

96kHz

——

24.5760

36.8640

49.1520

(1)

192kHz

24.5760

36.8640

(2)

NOTES: (1) The 768fS system clock rate is not supported for fS > 64kHz. (2) This system clock is not supported for the given sampling frequency.

TABLE I. System Clock Rates for Common Audio Sampling Frequencies.

SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)

SCKH

SCKL

System Clock Pulse Width HIGH t

SCKH: 7ns (min)

System Clock Pulse Width LOW t

SCKL: 7ns (min)

NOTE: (1) 1/128f

S, 1/256fS, 1/384fS, 1/512fS, and 1/768fS.

2.0V

0.8V

System Clock

Pulse Cycle Time(1)

PCM1608KY/2K датащи(PDF) 9 Page - Texas Instruments

PCM1608KY/2K датащи(HTML) 9 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

датащи скачать

ссылки URL