PCM3010

SLES055 – NOVEMBER 2002

26

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PCM audio interface (continued)

BCK

LRCK

DIN

tBCH

tBCL

tLRP

tLB

tBCY

1.4 V

1.4 V

1.4 V

tBL

DOUT

tCKDO

tLRDO

0.5 VDD

tDIS

tDIH

PARAMETER

MIN

MAX

UNIT

tBCY

BCK pulse cycle time

80

ns

tBCH

BCK pulse duration, HIGH

35

ns

tBCL

BCK pulse duration, LOW

35

ns

tBL

BCK rising edge to LRCK edge

10

ns

tLB

LRCK edge to BCK rising edge

10

ns

tLRP

LRCK pulse duration

2.1

µs

tDIS

DIN setup time

10

ns

tDIH

DIN hold time

10

ns

tCKDO

DOUT delay time from BCK falling edge

20

ns

tLRDO

DOUT delay time from LRCK edge

20

ns

tR

Rising time of all signals

10

ns

tF

Falling time of all signals

10

ns

Figure 49. Audio Data Input/Output Timing

synchronization with digital audio system

The PCM3010 operates with LRCK and BCK synchronized to the system clock. The PCM3010 does not need

a specific phase relationship between LRCK, BCK and the system clock, but does require the synchronization

of LRCK, BCK, and the system clock.

If the relationship between system clock and LRCK changes more than

±6 BCKs during one sample period due

In the case of changes less than

±5 BCKs, resynchronization does not occur and the previously described

discontinuity in analog/digital output control does not occur.