TNETX3150A datasheet(75/113 Pages) TI1

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TNETX3150/TNETX3150A

ThunderSWITCH™ 15-PORT 10-/100-MBIT/S ETHERNET™ SWITCH

SPWS027F – FEBRUARY 1997 – REVISED SEPTEMBER 1997

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

secondary test access: internal RAM access modes

When implementing an architecture that employs embedded RAM structures, it is necessary to ensure test

access over and above JTAG connectivity testing through standard interfacing. The DIO interface used by the

TNETX3150/TNETX3150A

enables

the

user

interrogate

the

internal

RAMS

the

TNETX3150/TNETX3150A. User interrogation gives the required observability for the RAM and the data they

contain.

RAM test access is desirable at all levels of testing:

• Silicon production level that enables detection of defective devices

• System production level that permits diagnostic testing

• Field level that permits diagnostics and debugging

FIFO RAM test access

FIFO RAM access for test is provided through the DIO interface. This allows full RAM access for RAM testing

purposes. Access to the FIFO shall be allowed only following a soft reset and before the START bit is written

(or after power up and before the START bit is written). The soft reset bit should be set, then immediately reset.

If the soft reset bit is not cleared, the TNETX3150/TNETX3150A holds the DRAM refresh logic operation in reset

and the contents of the external memory becomes invalid.

To access the FIFO RAM from the DIO, bytes are written to a holding latch that is the width of the RAM word

(72 bits). When a byte is accessed, the whole word is updated in RAM. If the same pattern is to be loaded

throughout the memory, it requires only a new FIFO RAM address for setup between accesses on a single byte

within the word. The data in the latch does not change (i.e., a read /modify/write is not performed).

structure (statistics) RAM test access

Test access to the statistics RAM is provided through the DIO port after the TNETX3150/TNETX3150A is soft

reset (or following power up before the start bit is set). In this mode, all locations of the RAM can be written to

and read from. Once the start bit is set, only read access is permitted to the RAM. When asserting soft reset,

it is important to reset the soft reset bit immediately after setting it. This ensures that the DRAM refresh logic

operation is not held at reset. If held at reset, normal DRAM refreshes fail to occur, and the DRAM contents

become invalid.

To access the structure RAM from the DIO, bytes are written to a holding latch that is the width of the RAM word

(64 bits). When a byte is accessed, the whole word is updated in RAM. If the same pattern is loaded throughout

the memory, it requires only a new structure RAM address for setup between accesses on a single byte within

the word. The data in the latch does not change (i.e., a read/modify/write is not performed).

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