HV2802/HV2902

DS20005449A-page 8

 2015 Microchip Technology Inc.

1.1

Logic Timing and Truth Table

FIGURE 1-1:

Logic Timing Waveforms.

TABLE 1-1:

TRUTH TABLE (Notes 1 — 6)

D0

D1

•••

D15

D16

•••

D31

LE

CLR

SW0

SW1

•••

SW15 SW16

•••

SW31

L—

•••

——

•••

—L

L

OFF

—

•••

——

•••

—

H—

—

—

—

L

L

ON

—

—

—

—

—L

—

—

—

L

L—

OFF

—

—

—

—H

—

—

—

L

L

—

ON

—

—

—

—

—

—

—

—

L

L

—

——

——

—

—

—

—

—

L

L

—

——

——

—

—

L—

—

L

L—

—

OFF

—

—

——

H

—

—

L

L

—

—

ON

—

—

——

—

L

—

L

L

—

—

—

OFF

—

——

—

H

—

L

L

—

—

—

ON

—

—

—

—

—

—

L

L

—

——

——

—

—

—

—

—

L

L

—

——

——

—

—

—

—

—

L

L

—

——

——

—

—

—

—

—

L

L

—

——

——

——

—

—

L

L

L

—

—

—

—

OFF

——

—

—

H

L

L

—

—

—

—

ON

X

X

X

X

X

X

X

H

L

HOLD PREVIOUS STATE

X

X

X

X

X

X

X

X

H

ALL SWITCHES OFF

Legend:

X = Do not care; L = Low; H = High.

Note 1:

The 32 switches operate independently.

2:

Serial data is clocked in on the L to H transition of the CLK.

3:

All 32 switches go to a state retaining their latched condition at the rising edge of LE. When LE is low, the

shift register’s data flow through the latch.

4:

5:

Shift register’s clocking has no effect on the switch states if LE is high.

6:

The CLR clear input overrides all other inputs.

50%

50%

50%

50%

50%

50%

50%

50%

10%

50%

10%

DATA

IN

LE

CLOCK

DATA

OUT

OFF

ON

CLR

(typical)

50%