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DS20005412A-page 13

HV7351

2.0

PIN DESCRIPTION

The descriptions of the pins are listed in Table 2-1.

TABLE 2-1:

PIN FUNCTION TABLE

Pin

Symbol

Description

Positive analog supply voltage (+5.0V)

2

DIN2

Serial data in for delay counters and frequency divider

3CS2

Activates DIN2. Input logic high = off, input logic low = on.

4

SIZE

Sets pattern width to either 16-bits or 32-bits. Logic low = 16-bits, logic high = 32-bits.

5

INV

Inverts the TX output waveform. See Table 1-3 for details.

6

CW

Activates CW mode. Logic low = non-CW mode, logic high = CW mode.

See Table 1-3 for details.

7

DOUT2

Data out for delay counters and frequency divider

8

EN

Enables and disables device. Logic low = off, logic high = on.

9

SCK

Serial clock input for serial shift registers

10, 50

Positive digital supply voltage (+5.0V)

11, 43, 51, 58

Digital ground

12

TRIG

Toggles all TX outputs to transmit. Needs to be high for two rising edges of TCK.

Delay counters will start on the rising edge of the TCK pin right after the falling edge of

the TRIG signal. See Section 1.1 “Timing Diagrams” for details.

13

TCK

The TCK and TCK pins can be driven by LVDS or SSTL types of output in a

differential manner. The TCK pin can be driven by LVCMOS single-ended output,

while setting the TCK to GND (or DC value of 0.4V to 0.6V). The logic trip point is on

the TCK rising edge and on the TCK falling edge, crossing in the differential manner.

In the single-ended case, the trip point is on the TCK rising edge.

14

TCK

15

Logic interface supply voltage (3.3V)

16

CS1

Activates DIN1. Input logic high = off, input logic low = on

17

DOUT1

Data out for P-Channel and N-Channel pattern registers

18

A0

Decoded to select 1 of 4 patterns to be loaded

19

A1

20

DIN1

Serial data in for P-Channel and N-Channel pattern registers

21

22, 49, 52, 79

Positive gate drive supply voltage for RTZ output transistors (+5.0V)

23, 24, 46, 48,

53, 55, 77, 78

Power ground path for RTZ output transistors

25, 47, 54, 76

Negative gate drive supply voltage for RTZ output transistors (-5.0V)

26, 45, 56, 75

Linear regulator output gate drive voltage for the P-Channel output transistors. A low

pins. There are four capacitors required in total.

27

NC

No connection

28, 42, 59, 73

Linear regulator output gate drive voltage for the N-Channel output transistors. A low

pins. There are four capacitors required in total.

29, 34, 35, 40,

41, 60, 61, 66,

67, 72

Negative high voltage supply (-3.0V to -70V)

30

TX1

Transmit pulser outputs for channel 1

31, 32, 37, 38,

44, 57, 63, 64,

69, 70

Positive high voltage supply (+3.0V to +70V)