AD7490BCP datasheet(15/24 Pages) AD

15 / 24 page

AD7490

–15–

REV. A

SCLK

DOUT

DIN

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

CONTROL REGISTER IS LOADED ON THE

FIRST 12 CLOCKS, PM1

1, PM0

DATA IN TO CONTROL REGISTER

TO KEEP PART IN NORMAL MODE, LOAD

PM1

1, PM0

1 IN CONTROL REGISTER

PART IS FULLY POWERED UP

ONCE TPOWER UP HAS ELAPSED

PART BEGINS TO POWER UP ON

RISING EDGE AS PM1

1, PM0

DATA IN TO CONTROL/SHADOW REGISTER

PART IS IN FULL

SHUTDOWN

t12

Figure 13. Full Shutdown Mode Operation

SCLK

DOUT

DIN

116

DUMMY CONVERSION

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

INVALID DATA

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

DATA IN TO CONTROL/SHADOW REGISTER

PART ENTERS

SHUTDOWN ON

RISING EDGE AS

PM1

0, PM0

CONTROL REGISTER IS LOADED ON THE

FIRST 12 CLOCKS, PM1

0, PM0

DATA IN TO CONTROL/SHADOW REGISTER

CONTROL REGISTER CONTENTS SHOULD

NOT CHANGE, WRITE BIT

TO KEEP PART IN THIS MODE, LOAD PM1

0, PM0

IN CONTROL REGISTER OR SET WRITE BIT = 0

PART IS FULLY

POWERED UP

PART BEGINS

TO POWER

UP ON

FALLING EDGE

PART ENTERS

SHUTDOWN ON

RISING EDGE AS

PM1

0, PM0

Figure 14. Auto Shutdown Mode Operation

Normal Mode (PM1 = PM0 = 1)

This mode is intended for the fastest throughput rate performance

as the user does not have to worry about any power-up times with

the AD7490 remaining fully powered at all times. Figure 12 shows

the general diagram of the operation of the AD7490 in this mode.

SCLK

DOUT

DIN

CHANNEL IDENTIFIER BITS + CONVERSION RESULT

NOTES

1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES

2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES

DATA IN TO CONTROL/SHADOW REGISTER

Figure 12. Normal Mode Operation

The conversion is initiated on the falling edge of

CS and the track

and hold will enter hold mode as described in the Serial Interface

section. The data presented to the AD7490 on the DIN line during

the first 12 clock cycles of the data transfer is loaded to the

Control Register (provided WRITE Bit is 1). If data is to be written to

the Shadow Register (SEQ

0, SHADOW

1 on previous write),

data presented on the DIN line during the first 16 SCLK cycles is

loaded into the Shadow Register. The part will remain fully powered

up in Normal Mode at the end of the conversion as long as PM1

and PM0 are set to 1 in the write transfer during that conversion.

To ensure continued operation in Normal Mode, PM1 and PM0 are

both loaded with 1 on every data transfer. Sixteen serial clock

cycles are required to complete the conversion and access the

conversion result. The track and hold will go back into track on

the 14th SCLK falling edge.

CS may then idle high until the next

conversion or may idle low until sometime prior to the next

conversion, (effectively idling

CS low).

Once a data transfer is complete (DOUT has returned to three-

state WEAK/

TRI Bit

0), another conversion can be initiated

after the quiet time, tQUIET, has elapsed by bringing CS low again.

Full Shutdown (PM1 = 1, PM0 = 0)

In this mode, all internal circuitry on the AD7490 is powered

down. The part retains information in the Control Register during

full shutdown. The AD7490 remains in full shutdown until

the power management bits in the Control Register, PM1 and

PM0, are changed.

If a write to the Control Register occurs while the part is in Full

Shutdown, with the power management bits changed to PM0 =

PM1 = 1, Normal Mode, the part will begin to power up on the

rising edge. The track and hold that was in hold while the part was

in Full Shutdown will return to track on the 14th SCLK falling edge.

To ensure that the part is fully powered up, tPOWER UP (t12)

should have elapsed before the next

CS falling edge. Figure 13

shows the general diagram for this sequence.

Auto Shutdown (PM1 = 0, PM0 = 1)

In this mode, the AD7490 automatically enters shutdown at the

end of each conversion when the Control Register is updated.

When the part is in shutdown, the track and hold is in hold mode.

Figure 14 shows the general diagram of the operation of the

AD7490BCP датащи(PDF) 15 Page - Analog Devices

AD7490BCP датащи(HTML) 15 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

датащи скачать

ссылки URL