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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TNETV2840ENGGU датащи(PDF) 39 Page - Texas Instruments |
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TNETV2840ENGGU датащи(HTML) 39 Page - Texas Instruments |
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39 / 91 page  Functional Overview 39 December 1999 − Revised October 2008 SPRS122F 3.2.3 Multichannel Buffered Serial Port (McBSP) The 5441 device provides high-speed, full-duplex serial ports that allow direct interface to other C54x/LC54x devices, codecs, and other devices in a system. There are twelve multichannel buffered serial ports (McBSPs) on chip (three per subsystem). The McBSP provides: • Full-duplex communication • Double-buffer data registers, which allow a continuous data stream • Independent framing and clocking for receive and transmit In addition, the McBSP has the following capabilities: • Direct interface to: − T1/E1 framers − MVIP switching-compatible and ST-BUS compliant devices − IOM-2 compliant device − AC97-compliant device − Serial peripheral interface (SPI) • Multichannel transmit and receive of up to 128 channels • A wide selection of data sizes, including: 8, 12, 16, 20, 24, or 32 bits •µ-law and A-law companding • Programmable polarity for both frame synchronization and data clocks • Programmable internal clock and frame generation 3.2.3.1 McBSP Clock Source The 5441 McBSPs allow either the receive clock pin (BCLKRn) or the transmit clock pin (BCLKXn) to be configured as the input clock to the sample rate generator. This enhancement is enabled through two register bits: bit 7 [the enhanced sample clock mode bit (SCLKME)] of the pin control register (PCR), and bit 13 [the McBSP sample rate generator clock mode bit (CLKSM)] of the sample rate generator register 2 (SRGR2). SCLKME is an addition to the PCR contained in the McBSPs on previous TMS320C5000 DSP platform devices. The new bit layout of the PCR is shown in Figure 3−15. For a description of the remaining bits, see TMS320C54x DSP Reference Set, Volume 5: Enhanced Peripherals (literature number SPRU302). 15 14 13 12 11 10 9 8 Reserved XIOEN RIOEN FSXM FSRM CLKXM CLKRM R,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 RW,+0 7 6 54 3 210 SCLKME CLKS_STAT DX_STAT DR_STAT FSXP FSRP CLKXP CLKRP RW,+0 R,+0 R,+0 R,+0 RW,+0 RW,+0 RW,+0 RW,+0 LEGEND: R = Read, W = Write, +0 = Value at reset Figure 3−15. Pin Control Register (PCR) TMS320C5000 is a trademark of Texas Instruments. |
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