MSP430x41x

MIXED SIGNAL MICROCONTROLLER

SLAS340G − MAY 2001 − REVISED JUNE 2004

23

POST OFFICE BOX 655303

electrical characteristics over recommended operating free-air temperature (unless otherwise

noted) (continued)

Schmitt-trigger inputs − Ports P1, P2, P3, P4, P5, and P6

PARAMETER

VCC

MIN

TYP

MAX

UNIT

VIT+

Positive-going input threshold voltage

2.2 V

1.1

1.5

V

VIT+

Positive-going input threshold voltage

3 V

1.5

1.9

V

VIT−

Negative-going input threshold voltage

2.2 V

0.4

0.9

V

VIT−

Negative-going input threshold voltage

3 V

0.9

1.3

V

Vhys

Input voltage hysteresis (VIT+ − VIT−)

2.2 V

0.3

1.1

V

Vhys

Input voltage hysteresis (VIT+ − VIT−)

3 V

0.45

1

V

standard inputs − RST/NMI; JTAG: TCK, TMS, TDI/TCLK, TDO/TDI

PARAMETER

VCC

MIN

TYP

MAX

UNIT

VIL

Low-level input voltage

2.2 V/3 V

VSS

VSS+0.6

V

VIH

High-level input voltage

2.2 V/3 V

0.8

×VCC

VCC

V

inputs Px.x, TAx/TAx.x

PARAMETER

TEST CONDITIONS

VCC

MIN

TYP

MAX

UNIT

Port P1, P2: P1.x to P2.x, External

2.2 V/3 V

1.5

cycle

t(int)

External interrupt timing

Port P1, P2: P1.x to P2.x, External

trigger signal for the interrupt flag,

(see Note 1)

2.2 V

62

ns

t(int)

External interrupt timing

trigger signal for the interrupt flag,

(see Note 1)

3 V

50

ns

t(cap)

Timer_A, capture timing

TAx/TAx.y

2.2 V

62

ns

t(cap)

Timer_A, capture timing

TAx/TAx.y

3 V

50

ns

f(TAext)

Timer_A clock frequency externally

TACLK/TAxCLK, INCLK t(H) = t(L)

2.2 V

8

MHz

f(TAext)

Timer_A clock frequency externally

applied to pin

TACLK/TAxCLK, INCLK t(H) = t(L)

3 V

10

MHz

f(TAint)

Timer_A clock frequency

SMCLK or ACLK signal selected

2.2 V

8

MHz

f(TAint)

Timer_A clock frequency

SMCLK or ACLK signal selected

3 V

10

MHz

NOTES:

1. The external signal sets the interrupt flag every time the minimum t(int) cycle and time parameters are met. It may be set even with

trigger signals shorter than t(int). Both the cycle and timing specifications must be met to ensure the flag is set. t(int) is measured in

MCLK cycles.

leakage current (see Note 1)

PARAMETER

TEST CONDITIONS

VCC

MIN

NOM

MAX

UNIT

Ilkg(P1.x)

Leakage current

Port P1

V(P1.x) (see Note 2)

2.2 V/3 V

±50

nA

Ilkg(P6.x)

Leakage current

Port P6

V(P6.x) (see Note 2)

2.2 V/3 V

±50

nA

NOTES:

1. The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.

2. The port pin must be selected as an input.