TM8LR64JFN 8 388 608 BY 64BIT

TM16LR64JFN 16 777 216 BY 64BIT

SYNCHRONOUS DYNAMIC RAM MODULES

SMMS710 − MAY 1998

6

POST OFFICE BOX 1443

−0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range on any pin (see Note 1)

− 0.5 V to 4.6 V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Short-circuit output current

50 mA

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power dissipation: TM8LR64JFN

8 W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TM16LR64JFN

16 W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0

°C to 70°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

− 55

°C to 150°C

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to VSS.

recommended operating conditions

MIN

NOM

MAX

UNIT

VDD

Supply voltage

3

3.3

3.6

V

VSS

Supply voltage

0

V

VIH

High-level input voltage

2

VDD + 0.3

V

VIH-SPD High-level input voltage for SPD device

2

5.5

V

VIL

Low-level input voltage

−0.3

0.8

V

TA

Ambient temperature

0

70

°C

capacitance

over recommended ranges of supply voltage and ambient temperature,

PARAMETER

’xLR64JFN

UNIT

PARAMETER

MIN

MAX

UNIT

Ci(CK)

Input capacitance, CK input

2.5

4

pF

Ci(AC)

Input capacitance, address and control inputs: A0 − A13, RAS, CAS, WE

2.5

5

pF

Ci(CKE)

Input capacitance, CKE input

5

pF

Co

Output capacitance

4

6.5

pF

Ci(DQMBx)

Input capacitance, DQMBx input

2.5

5

pF

Ci(Sx)

Input capacitance, Sx input

2.5

5

pF

Ci/o(SDA)

SDA input/output capacitance

9

pF

Ci(SPD)

Input capacitance, SA0, SA1, SA2, SCL inputs

7

pF

‡ Specifications in this table represent a single SDRAM device.

NOTE 2: VDD = 3.3 V ± 0.3 V. Bias on pins under test is 0 V.