THS3091 datasheet(21/31 Pages) TI

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−VS

49.9

Ω

5.11

Ω

µF

249

Ω

27 pF

1 k

Ω

100-

Ω LOAD

FIN

−VS

866

Ω

866

Ω

191

Ω

5.11

Ω

5.11

Ω

SAVING POWER WITH POWER-DOWN

−VS

1 k

Ω

5.11

Ω

249

Ω

−VS

1 k

Ω

5.11

Ω

249

Ω

24.9

Ω

24.9

Ω

1 nF

THS3091

THS3095

SLOS423C – SEPTEMBER 2003 – REVISED AUGUST 2004

Figure 67.

Figure 68 is shown using two amplifiers in parallel to

Figure 69. PowerFET Drive Circuit

double the output drive current to larger capacitive

loads. This technique is used when more output

current is needed to charge and discharge the load

faster like when driving large FET transistors.

FUNCTIONALITY AND SETTING

THRESHOLD LEVELS WITH THE

REFERENCE PIN

The THS3095 features a power-down pin (PD) which

lowers the quiescent current from 9.5 mA down to

500 µA, ideal for reducing system power.

The power-down pin of the amplifier defaults to the

negative supply voltage in the absence of an applied

voltage, putting the amplifier in the power-on mode of

operation. To turn off the amplifier in an effort to

conserve power, the power-down pin can be driven

towards the positive rail. The threshold voltages for

power-on and power-down are relative to the supply

rails and are given in the specification tables. Below

the Enable Threshold Voltage, the device is on.

Figure 68.

Above the Disable Threshold Voltage, the device is

off. Behavior in between these threshold voltages is

Figure 69 shows a push-pull FET driver circuit typical

not specified.

of ultrasound applications with isolation resistors to

Note that this power-down functionality is just that;

isolate the gate capacitance from the amplifier.

the amplifier consumes less power in power-down

mode. The power-down mode is not intended to

provide a high-impedance output. In other words, the

power-down functionality is not intended to allow use

as a 3-state bus driver. When in power-down mode,

the impedance looking back into the output of the

amplifier

dominated

the

feedback

and

gain-setting resistors, but the output impedance of the

device itself varies depending on the voltage applied

to the outputs.

Figure 70 shows the total system output impedance

which includes the amplifier output impedance in

parallel with the feedback plus gain resistors, which

cumulate to 2380

Ω. Figure 59 shows this circuit

configuration for reference.

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