TLV5580

8BIT, 80 MSPS LOW POWER A/D CONVERTER

SLAS205B − DECEMBER 1998 − REVISED OCTOBER 2003

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PRINCIPLE OF OPERATION

The TLV5580 implements a high-speed 80 MSPS converter in a cost-effective CMOS process. Powered from

3.3 V, the single-pipeline design architecture ensures low-power operation and 8 bit accuracy. Signal input and

clock signals are all single-ended. The digital inputs are 3.3 V TTL / CMOS compatible. Internal voltage

references are included for both bottom and top voltages. Therefore the converter forms a self-contained

solution. Alternatively the user may apply externally generated reference voltages. In doing so, both input offset

and input range can be modified to suit the application.

A high-speed sampling-and-hold captures the analog input signal. Multiple stages will generate the output code

with a pipeline delay of 4.5 CLK cycles. Correction logic combines the multistage data and aligns the 8-bit output

word. All digital logic operates at the rising edge of CLK.

ANALOG INPUT

AIN

CI

S1

RSW

RS

VS

TLV5580

Figure 12. Simplified Equivalent Input Circuit

A first-order approximation for the equivalent analog input circuit of the TLV5580 is shown in Figure 12. The

sample period of one half clock cycle. When a full-scale voltage step is applied, the input source provides the

capacitor requires no input current and the equivalent input impedance is very high.

To maintain the frequency performance outlined in the specifications, the total source impedance should be

limited to about 80

R

S t

1

÷ 2f

CLK

C

I

In(256) –R

SW