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K28.5

DXX.X

K28.5

DXX.X

DXX.X

DXX.X

DXX.X

DXX.X

K28.5

K28.5

DXX.X

Bits 0-4 Bits 5-9

RBC0

SYNC

RD(0-4)

Receiver Word Alignment

Comma Character on Expected Boundary

Comma Character Not on Expected Boundary

TLK1201ARCP, TLK1201AIRCP

ETHERNET TRANSCEIVERS

SLLS580D – FEBRUARY 2004 – REVISED SEPTEMBER 2007

Figure 4. Synchronous Timing Characteristics Waveforms (DDR Mode)

The receiver clock interpolator can lock to the incoming data without the need for a lock-to-reference preset. The

received serial data rate (RXP and RXN) is at the same baud rate as the transmitted data stream, 0.02% (200

PPM) for proper operation (see the recommended operating tables).

This device uses the IEEE 802.3 gigabit ethernet defined 10-bit K28.5 character (comma character) word

alignment scheme. The following sections explain how this scheme works and how it realigns itself.

This device provides 10-bit K28.5 character recognition and word alignment. The 10-bit word alignment is

enabled by forcing the SYNCEN terminal high. This enables the function that examines and compares serial

input data to the 7-bit synchronization pattern. The K28.5 character is defined by 8-bit/10-bit coding scheme as a

pattern consisting of 0011111010 (a negative number beginning with disparity) with the 7 MSBs (0011111),

referred to as the comma character. The K28.5 character was implemented specifically for aligning data words.

As long as the K28.5 character falls within the expected 10-bit boundary, the received 10-bit data is properly

aligned and data realignment is not required. Figure 2 shows the timing characteristics of RBC0, RBC1, SYNC,

and RD0–RD9 while synchronized. (Note: the K28.5 character is valid on the rising edge of RBC1.)

If synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then word

realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character following the

misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown in Figure 5. The

RBC0 and RBC1 pulse widths are stretched or stalled in their current state during realignment. With this design,

the maximum stretch that occurs is 20 bit times. This occurs during a worst case scenario when the K28.5 is

aligned to the falling edge of RBC1 instead of the rising edge. Figure 5 shows the timing characteristics of the

data realignment.

Copyright © 2004–2007, Texas Instruments Incorporated

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