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LP8720 датащи(PDF) 5 Page - Texas Instruments |
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LP8720 датащи(HTML) 5 Page - Texas Instruments |
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5 / 26 page ![]() EN LDO1 0 1 2 3 4 5 6 7 LDO2 tBON tS Timing Code Timing Code START UP sequence SHUT DOWN sequence is in reverse order of START UP sequence EN LDO1 0 1 2 3 4 5 6 7 LDO2 LDO3 LDO3 LDO4 LDO4 LDO5 LDO5 BUCK BUCK STANDBY START UP tS tS tS tS tS tS tS tS tS tS tS tS tS SHUT DOWN STANDBY IDLE Note 3 Note 3 Note 3 Note 3 Note 3 Note 4 Note 5 LP8720 www.ti.com SNVS575B – JULY 2008 – REVISED MAY 2013 tBON 150 µs – Reference and bias turn ON. Min 100 µs max 200 µs. tS 25 µs – time step. Time step accuracy is defined by OSC frequency accuracy. (1) STARTUP and SHUTDOWN sequences are defined by registers. Sequences given here are valid if there the registers are not rewritten via Serial Interface. (2) The timing showed here define time points when LDO’s and BUCK are enabled/disabled. Enabling /disabling process duration depends on loading conditions. Buck startup duration is 140 µs for no load. LDO startup duration is no more than 35 µs. For details please see LDO’s and BUCK Electrical Specifications. (3) LDO1, LDO2, LDO4, LDO5 and BUCK are disabled. If LDO1, LDO2, LDO4, LDO5 and/or BUCK are enabled via Serial Interface and startup sequence is not changed via Serial interface, then LDO1, LDO2, LDO4, LDO5 and BUCK are disabled with no delay from falling edge on EN-pin. (4) At this time point registers 0x09 and 0x0C are reset to POR default values. (5) At this time point registers 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 and 0x08 are reset to POR default values. Figure 3. Startup Sequence if DEFSEL=GND Table 1. Startup Sequence(1) DEFSEL Startup Sequence Shutdown Sequence VBATT LDO1, 2, 3, 4 enable same time. In reverse order of startup sequence. LDO5 and BUCK enable via Serial Interface. GND LDO3 enable. In reverse order of startup sequence. LDO1, 2, 4, 5 and BUCK enable via Serial Interface . Hi-Z LDO1, 2, 3, 4 enable same time. In reverse order of startup sequence. LDO5 and BUCK enable via Serial Interface. (1) When IDSEL= VBATT then slave address is 7h’7F. When IDSEL= floating (Hi-Z) then slave address is 7h’7C. When IDSEL= GND then slave address is 7h’7D. Copyright © 2008–2013, Texas Instruments Incorporated Submit Documentation Feedback 5 Product Folder Links: LP8720 |
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