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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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LP8550TLX/NOPB датащи(PDF) 35 Page - Texas Instruments |
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LP8550TLX/NOPB датащи(HTML) 35 Page - Texas Instruments |
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35 / 49 page  LP8550 www.ti.com SNVS657E – SEPTEMBER 2010 – REVISED SEPTEMBER 2014 EEPROM ADDRESS 7 REGISTER HYSTERESIS 1:0 R/W PWM input hysteresis function. Defines how small changes in the PWM input are ignored to remove constant switching between two values. 00 = OFF 01 = 1-bit hysteresis with 11-bit resolution 10 = 1-bit hysteresis with 10-bit resolution 11 = 1-bit hysteresis with 8-bit resolution Table 7. PLL Value Calculation en_vsync PLL FREQUENCY [MHz] PLL[12:0] 0 5, 10, 20, 40 not used 5 5 MHz / (26 x fVSYNC) 10 10 MHz / (50 x fVSYNC) 1 20 20 MHz / (98 x fVSYNC) 40 40 MHz / (196 x fVSYNC) PLL frequency is set by PWM_RESOLUTION[1:0] bits. For Example: If fPLL = 5 MHz and fVSYNC = 60 Hz, then PLL[12:0] = 5000000 Hz / (26 * 60 Hz) = 3205d = C85h. If fPLL = 10 MHz and fVSYNC = 75 Hz, then PLL[12:0] = 10000000 Hz / (50 * 75 Hz) = 2667d = A6Bh. Copyright © 2010–2014, Texas Instruments Incorporated Submit Documentation Feedback 35 Product Folder Links: LP8550 |
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