LP5521 datasheet(34/48 Pages) TI1

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LP5521

SNVS441H – JANUARY 2007 – REVISED MAY 2016

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7.6.11 G Channel Program Counter Value (G Channel PC)

Address 0AH

Reset value 00H

Table 31. G Channel PC Register

G_PC[3]

G_PC[2]

G_PC[1]

G_PC[0]

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

G_PC

3:0

R/W

G channel program counter value

PC registers are synchronized to 32 kHz clock. Delay between consecutive I2C writes to PC registers needs to

be longer than 153

μs (typ.). PC register can be read or written only when EXEC mode is 'hold'.

7.6.12 B Channel Program Counter Value (B Channel PC)

Address 0BH

Reset value 00H

Table 32. B Channel PC Register

B_PC[3]

B_PC[2]

B_PC[1]

B_PC[0]

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

B_PC

3:0

R/W

B channel program counter value

PC registers are synchronized to a 32-kHz clock. Delay between consecutive I2C writes to PC registers must be

longer than 153

μs (typ.). PC register can be read or written only when EXEC mode is 'hold'.

7.6.13 Status/Interrupt Register

Address 0CH

Reset value 00H

Table 33. STATUS/INTERRUPT Register

EXT_CLK

USED

R_INT

G_INT

B_INT

NAME

BIT

ACCESS

ACTIVE

DESCRIPTION

EXT_CLK

USED

External clock state

0 = Internal 32kHz clock used

1 = External 32kHz clock used

R_INT

High

Interrupt from R channel

G_INT

High

Interrupt from G channel

B_INT

High

Interrupt from B channel

Note: Register INT bits will be cleared when read operation to Status/Interrupt register occurs. INT output pin

(active low) will go high after read operation.

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