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PCA8565 датащи(PDF) 17 Page - NXP Semiconductors |
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PCA8565 датащи(HTML) 17 Page - NXP Semiconductors |
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17 / 26 page ![]() Philips Semiconductors PCA8565 Real time clock/calender Product data Rev. 01 — 31 March 2003 17 of 26 9397 750 10695 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. 12. Dynamic characteristics [1] Unspecified for fCLKOUT = 32.768 kHz. [2] All timing values are valid within the operating supply voltage at ambient temperature and referenced to VIL and VIH with an input voltage swing of VSS to VDD. [3] A detailed description of the I2C-bus specification, with applications, is given in brochure The I2C-bus and how to use it. This brochure may be ordered using the code 9398 393 40011. [4] I2C-bus access time between two STARTs or between a START and a STOP condition to this device must be less than one second. Table 29: Dynamic characteristics VDD = 1.8 to 5.5 V; VSS =0V; Tamb = −40 to + 125 °C; fosc = 32.768 kHz; quartz Rs =40kΩ; CL = 8 pF; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Oscillator CINT integrated load capacitance 15 25 35 pF ∆fosc/fosc oscillator stability ∆V DD = 200 mV; Tamb =25 °C- 2 × 10-7 -- Quartz crystal parameters (f = 32.768 kHz) Rs series resistance - - 40 k Ω CL parallel load capacitance - 10 - pF CT trimmer capacitance 5 - 25 pF CLKOUT output δCLKOUT CLKOUT duty cycle [1] -50 - % Timing characteristics: I2C-bus[2][3] fSCL SCL clock frequency [4] - - 400 kHz tHD;STA START condition hold time 0.6 - - µs tSU;STA set-up time for a repeated START condition 0.6 - - µs tLOW SCL LOW time 1.3 - - µs tHIGH SCL HIGH time 0.6 - - µs tr SCL and SDA rise time - - 0.3 µs tf SCL and SDA fall time - - 0.3 µs Cb capacitive bus line load - - 400 pF tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns tSU;STO set-up time for STOP condition 0.6 - - µs tSW tolerable spike width on bus --50 ns |
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