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LP3952 датащи(PDF) 28 Page - Texas Instruments |
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LP3952 датащи(HTML) 28 Page - Texas Instruments |
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28 / 46 page ![]() SDA SCL 1 8 2 3 7 6 5 8 10 4 9 1 7 ack from slave msb Chip Address lsb ack from slave w msb Register Add lsb rs r msb DATA lsb stop ack from slave ack from master repeated start data from slave start Id = 54h w ack addr = h00 ack rs r ack Address 00h data ack stop msb Chip Address lsb Id = 54h start SCL SDA LP3952 SNVS518A – JULY 2007 – REVISED MARCH 2013 www.ti.com Figure 18. I2C Read Cycle Figure 19. I2C Timing Diagram I 2C Timing Parameters VDD1,2 = 3.0 to 4.5V, VDD_IO = 1.65V to VDD1,2 Limit Symbol Parameter Units Min Max 1 Hold Time (repeated) START Condition 0.6 μs 2 Clock Low Time 1.3 μs 3 Clock High Time 600 ns 4 Setup Time for a Repeated START Condition 600 ns 5 Data Hold Time (Output direction, delay generated by LP3952) 300 900 ns 5 Data Hold Time (Input direction, delay generated by the Master) 0 900 ns 6 Data Setup Time 100 ns 7 Rise Time of SDA and SCL 20+0.1Cb 300 ns 8 Fall Time of SDA and SCL 15+0.1Cb 300 ns 9 Set-up Time for STOP condition 600 ns 10 Bus Free Time between a STOP and a START Condition 1.3 μs Cb Capacitive Load for Each Bus Line 10 200 pF 28 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated Product Folder Links: LP3952 |
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