TLC5617, TLC5617A

PROGRAMMABLE DUAL 10-BIT DIGITAL-TO-ANALOG CONVERTERS

SLAS151B – JULY 1997 – REVISED MARCH 2000

5

POST OFFICE BOX 655303

digital inputs (DIN, SCLK, CS)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

IIH

High-level digital input current

VI = VDD

±1

µA

IIL

Low-level digital input current

VI = 0 V

±1

µA

Ci

Input capacitance

8

pF

power supply

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Supply voltage, VDD

4.5

5

5.5

V

IDD

Power supply current

VDD = 5.5 V,

No load

Slow

0.6

1

mA

IDD

Power supply current

No load,

All inputs = 0 V or VDD

Fast

1.6

2.5

mA

Power down supply current

D13 = 0 (see Table 3)

1

µA

analog output dynamic performance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

SR

Output slew rate

CL = 100 pF,

RL 10 kΩ

Vref(REFIN) = 2.048 V,

TA =25°C

Slow

0.3

0.5

V/

µs

SR

Output slew rate

RL = 10 kΩ,

Code 32 to Code 1024,

TA = 25°C,

VO from 10% to 90%

Fast

2.4

3

V/

µs

t

Output settling time

To

±0.5 LSB,

CL = 100 pF,

Slow

12.5

µs

ts

Output settling time

,

RL = 10 kΩ,

See Note 10

Fast

2.5

µs

t ()

Output settling time, code

To

±0.5 LSB,

CL = 100 pF,

Slow

2

µs

ts(c)

g,

to code

,

RL = 10 kΩ,

See Note 11

Fast

2

µs

Glitch energy

DIN = All 0s to all 1s,

f(SCLK) = 100 kHz

CS = VDD,

5

nV–s

S/(N+D)

Signal to noise + distortion

Vref(REFIN) = 1 Vpp at 1 kHz and 10 kHz + 1.024 V dc,

Slow

78

dB

S/(N+D)

Signal to noise + distortion

()

Input code = 10 0000 0000

Fast

81

dB

NOTES: 10. Settling time is the time for the output signal to remain within

±0.5 LSB of the final measured value for a digital input code change

of 020 hex to 3FF hex or 3FF hex to 020 hex.

11. Setting time is the time for the output signal to remain within

±0.5 LSB of the final measured value for a digital input code change

of one count.

digital input timing requirements

MIN

NOM

MAX

UNIT

tsu(DS)

Setup time, DIN before SCLK low

5

ns

th(DH)

Hold time, DIN valid after SCLK low

5

ns

tsu(CSS)

Setup time, CS low to SCLK low

5

ns

tsu(CS1)

Setup time, SCLK

↑ to CS ↑, external end-of-write

10

ns

tsu(CS2)

Setup time, SCLK

↑ to CS ↓, start of next write cycle

5

ns

tw(CL)

Pulse duration, SCLK low

25

ns

tw(CH)

Pulse duration, SCLK high

25

ns