WM8746

Advance Information

PP Rev 1.4 November 2001

11

RIGHT JUSTIFIED MODE

In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a

LRCIN

transition. LRCIN is high during the left samples and low during the right samples.

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN0/1/2

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB

Figure 5 Right Justified Mode TIming Diagram

I

In I

LRCIN is low during the left samples and high during the right samples.

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN0/1/2

1/fs

n

3

2

1

n-2 n-1

LSB

MSB

n

3

2

1

n-2 n-1

LSB

MSB

1 BCKIN

1 BCKIN

Figure 6 I

DSP EARLY MODE

In DSP early mode, the first bit is sampled on the BCKIN edge following the one which detects a low

to high transition on LRCIN.

1 BCKIN

LRCIN

BCKIN

DIN0

Input Word Length (IWL)

1/fs

CHANNEL 0

LEFT

n

2

1

n-1

LSB

MSB

n

2

1

n-1

CHANNEL 0

RIGHT

2

1

CHANNEL 1

LEFT

n

n-1

CHANNEL 2

RIGHT

NO VALID DATA

1 BCKIN

Figure 7 DSP Early Mode Timing Diagram