TAS3108 datasheet(8/63 Pages) TI1

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3.4 Power-On Reset (RESET)

3.5 Power Down (PDN)

3.6

2C Bus Control (CS0)

3.7

Programmable General Purpose I/O (GPIO)

3.7.1

No EEPROM is Present or a Memory Error Occurs

TAS3108, TAS3108IA

AUDIO DIGITAL SIGNAL PROCESSORS

SLES152B – OCTOBER 2005 – REVISED NOVEMBER 2007

As long as RESET is held LOW, the device is in the reset state. During reset, all I2C and serial data bus

operations are ignored. The I2C interface SCL and SDA lines go into a high-impedance state and remain

in that state until device initialization has completed.

The rising edge of the reset pulse begins the initialization housekeeping functions of clearing memory and

setting the default register values. Once these are complete, the TAS3108/TAS3108IA enables its master

I2C interface and disables its slave I2C interface.

Then the TAS3108/TAS3108IA looks for an EEPROM as described in Section 2.6, I2C Control Interface.

On power up, it is recommended that the TAS3108/TAS3108IA RESET be held LOW until DVDD has

reached 3.3 V. This can be done by programming the system controller or by using an external RC delay

circuit. The 1-k

Ω and 1-µF values provide a delay of approximately 200 µs. The values of R and C can be

adjusted to provide other delay values as necessary.

PDN is a user-firmware-definable pin that is programmed in the default TAS3108 and TAS3108IA

configuration to stop all clocks in the TAS3108/TAS3108IA, while preserving the state of the device. For

more information, see TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).

The TAS3108/TAS3108IA has a control to specify the slave and master I2C address. This control permits

up to two TAS3108/TAS3108IA devices to be placed in a system without external logic.

See Section 6.2 for a complete description of this pin.

The TAS3108/TAS3108IA has one GPIO pin that is 8051 firmware programmable.

On power up or following a reset, the GPIO pin becomes an input. Afterwards, the microprocessor can

program the GPIO as an input or an output.

For more information, see TAS3108/TAS3108IA Firmware Programmer's Guide (SLEU067).

Following reset or power-up initialization with the EEPROM not present or if a memory error occurs, the

TAS3108/TAS3108IA is in one of two modes, depending on the setting of the GPIO pin.

• GPIO pin is logic HIGH (through a 20-kΩ resistor)

With the GPIO pin held HIGH during initialization, the TAS3108/TAS3108IA comes up in the default

configuration with the serial data outputs not active. Once the TAS3108/TAS3108IA has completed

the default initialization procedure and after the status register is updated and the I2C slave

interface is enabled, the GPIO pin is an output and is driven LOW. Following the HIGH-to-LOW

transition of the GPIO pin, the system controller can access the TAS3108/TAS3108IA through the

I2C interface and read the status register to determine the load status.

If a memory-read error occurs, the TAS3108/TAS3108IA reports the error in the status register (I2C

subaddress 0x02).

• GPIO pin is logic LOW (through a 20-kΩ resistor)

With GPIO pin held LOW during initialization, the TAS3108/TAS3108IA comes up in an I/O test

configuration. In this case, once the TAS3108/TAS3108IA completes its default test initialization

procedure, the status register is updated, the I2C slave interface is enabled, and the

TAS3108/TAS3108IA streams audio unaltered from input to output as SDIN1 to SDOUT1, SDIN2 to

SDOUT2, etc.

In this configuration, the GPIO pin is an output signal that is driven LOW. If the external logic is no

Physical Characteristics

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