D7

D6

D5

D4

D3

D2

D1

D0

1

9

Ack

by

LMP91000

Start by

Master

No Ack

by

Master

SCL

SDA

Stop

by

Master

1

9

Frame 1

Serial Bus Address Byte

from Master

Frame 2

Data Byte from

Slave

R/W

A2

A0

A1

A3

A4

A5

A6

MENB

D7

D6

D5

D4

D3

D2

D1

D0

1

9

1

9

Ack

by

LMP91000

Start by

Master

R/W

Ack

by

LMP91000

Frame 1

Serial Bus Address Byte

from Master

Frame 2

Internal Address Register

Byte from Master

A2

A0

A1

A3

A4

A5

A6

SCL

SDA

Stop by

Master

MENB

LMP91000

www.ti.com

SNAS506I – JANUARY 2011 – REVISED DECEMBER 2014

Programming (continued)

Figure 28. Pointer Set Transaction

Figure 29. Register Read Transaction

7.6 Registers Maps

The registers are used to configure the LMP91000.

If writing to a reserved bit, user must write only 0. Readback value is unspecified and should be discarded.

Table 2. Register Map

Address

Name

Power on default

Access

Lockable?

0x00

STATUS

0x00

Read only

No

0x01

LOCK

0x01

R/W

No

0x02 through 0x09

RESERVED

—

—

—

0x10

TIACN

0x03

R/W

Yes

0x11

REFCN

0x20

R/W

Yes

0x12

MODECN

0x00

R/W

No

0x13 through 0xFF

RESERVED

—

—

—

7.6.1 STATUS -- Status Register (Address 0x00)

The status bit is an indication of the LMP91000's power-on status. If its readback is “0”, the LMP91000 is not

Bit

Name

Function

[7:1]

RESERVED

Status of Device

0

STATUS

0 Not Ready (default)

1 Ready

7.6.2 LOCK -- Protection Register (Address 0x01)

The lock bit enables and disables the writing of the TIACN and the REFCN registers. In order to change the

content of the TIACN and the REFCN registers the lock bit needs to be set to “0”.

Copyright © 2011–2014, Texas Instruments Incorporated

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